| A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 43rd annual conference on Design automation
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San Francisco, CA, USA
SESSION: Session 58: advanced methods for interconnect extraction, clocks and reliability
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Pages: 1053 - 1056
Year of Publication: 2006
ISBN:1-59593-381-6
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Downloads (6 Weeks): 3, Downloads (12 Months): 37, Citation Count: 0
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ABSTRACT
Simulation of distributed electromagnetic effects of electrically large structures is no longer a luxury but a necessity in the accurate prediction of modern day circuit performance. In this regard, integral equation based methods have steadily gained in popularity but suffer from the time and memory bottlenecks arising from the resultant dense matrix. Fast linear complexity solvers have been introduced in the past but with the growing complexity of circuit layouts parallel implementations are the only viable options in addressing practical circuit layouts. In this paper, we present a parallel implementation of the low-rank compression based fast solver with linear cost reduction capacity with respect to the number of processors. The main problems in parallelizing a hierarchical algorithm are discussed and the advantages of the implemented scheme are highlighted. The new solver enables the simulation of full-chip problems consisting of millions of unknowns with acceptable accuracy and modest time and memory requirements.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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