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A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual conference on Design automation table of contents
San Francisco, CA, USA
SESSION: Session 58: advanced methods for interconnect extraction, clocks and reliability table of contents
Pages: 1053 - 1056  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Chuanyi Yang  University of Washington, Seattle, WA
Swagato Chakraborty  University of Washington, Seattle, WA
Dipanjan Gope  University of Washington, Seattle, WA
Vikram Jandhyala  University of Washington, Seattle, WA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Simulation of distributed electromagnetic effects of electrically large structures is no longer a luxury but a necessity in the accurate prediction of modern day circuit performance. In this regard, integral equation based methods have steadily gained in popularity but suffer from the time and memory bottlenecks arising from the resultant dense matrix. Fast linear complexity solvers have been introduced in the past but with the growing complexity of circuit layouts parallel implementations are the only viable options in addressing practical circuit layouts. In this paper, we present a parallel implementation of the low-rank compression based fast solver with linear cost reduction capacity with respect to the number of processors. The main problems in parallelizing a hierarchical algorithm are discussed and the advantages of the implemented scheme are highlighted. The new solver enables the simulation of full-chip problems consisting of millions of unknowns with acceptable accuracy and modest time and memory requirements.


REFERENCES

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D.Gope and V.Jandhyala, "Oct-Tree Based Multilevel Low-Rank Decomposition Algorithm for Rapid 3D Parasitic Extraction", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol-23, pp. 1575 -- 1580, Nov. 2004.

Collaborative Colleagues:
Chuanyi Yang: colleagues
Swagato Chakraborty: colleagues
Dipanjan Gope: colleagues
Vikram Jandhyala: colleagues