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Translating between itanium and sparc memory consistency models

Published: 30 July 2006 Publication History

Abstract

Our general goal is to port programs from one multiprocessor architecture to another, while ensuring that each program's semantics remains unchanged. This paper addresses a subset of the problem by determining the relationships between memory consistency models of three Sparc architectures, (TSO, PSO and RMO) and that of the Itanium architecture. First we consider Itanium programs that are constrained to have only one load-type of instruction in {load, load _acquire}, and one store-type of instruction in {store, store_release}. We prove that in three out of four cases, the set of computations of any such program is exactly the set of computations of the "same" program (using only load and store) on one Sparc architecture. In the remaining case the set is nested between two natural sets of Sparc computations.Real Itanium programs, however, use a mixture of load, load acquire, store, store release and memory fence instructions, and real Sparc programs use a variety of barrier instruction as well as load and store instructions. We next show that any mixture of the loadtypes or the store-types (in the case of Itanium) or any barrier instructions (in the case of Sparc) completely destroys the clean and simple similarities between the sets of computations of these systems. Thus (even without considering the additional complications due to register and control dependencies) transforming these more general programs in either direction requires constraining the transformed program substantially more than the original program in order to ensure that no erroneous computations can arise.

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cover image ACM Conferences
SPAA '06: Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
July 2006
344 pages
ISBN:1595934529
DOI:10.1145/1148109
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 July 2006

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Author Tags

  1. itanium
  2. memory consistency models
  3. multiprocessors
  4. program transformations
  5. sparc

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SPAA06
SPAA06: 18th ACM Symposium on Parallelism in Algorithms and Architectures 2006
July 30 - August 2, 2006
Massachusetts, Cambridge, USA

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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  • (2018)Partition consistencyDistributed Computing10.1007/s00446-013-0205-027:5(363-389)Online publication date: 26-Dec-2018
  • (2015)ArMORACM SIGARCH Computer Architecture News10.1145/2872887.275037843:3S(388-400)Online publication date: 13-Jun-2015
  • (2015)ArMORProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750378(388-400)Online publication date: 13-Jun-2015
  • (2006)Programmer-centric conditions for itanium memory consistencyProceedings of the 8th international conference on Distributed Computing and Networking10.1007/11947950_7(58-69)Online publication date: 27-Dec-2006

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