Infrastructure for dynamic reconfigurable systems: choices and trade-offs

ABSTRACT

Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architectures might furnish enough performance for several classes of embedded systems. An associated advantage of these architectures is flexibility at the software level. In principle, hardware is not flexible. Thus, dedicated IP blocks must be inserted before chip design, or enough area can be reserved for them when using reconfigurable blocks. Dynamic self-reconfigurable systems (DSRSs) introduce flexibility to hardware. In DSRSs, IP blocks are loaded according to application demand, reducing area, power consumption and system cost. An MPSoC based platform, associated with dynamic reconfiguration, provides both hardware and software flexibility. This paper has two main goals. First, to present the necessary infrastructure for DSRSs, identifying which components are required in these systems, such as a configuration controller, configuration ports and reconfigurable IP interfaces. The second objective is to discuss practical implementations choices and area-performance tradeoffs. The paper employs case studies to access the advantages and problems related to different implementations for the communication infrastructure (bus and NoC), the configuration controller (hardware and software) and IP interfaces (LUT and tristate based).

REFERENCES

• 1: Keutzer, K.; et al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design". IEEE Transactions on CAD of Integrated Circuits and Systems, v. 19(12), pp. 1523--1543, 2000.
• 2: Wirthlin, M.; Hutchings, B. "Improving Functional Density Through Run-Time Constant Propagation". In: FPGA'97, pp. 86--92.
• 3: Ullmann, M.; et al. "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration". In: IPDPS'04, pp. 135--142.
• 4: Resano, J.; et al. "Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware". In: DAC'04, pp. 119--121.
• 5: Mignolet, J.; et al. "Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip". In: DATE'03, pp. 986--991.
• 6: Griese, B.; et al. "Hardware Support for Dynamic reconfiguration in Reconfigurable SoC Architectures". In: FPL'04, pp. 842--846.
• 7: Carvalho, E.; Calazans, N.; Moraes, F.; Mesquita, D. "Reconfiguration Control for Dynamically Reconfigurable Systems". In: DCIS'04, pp 405--410.
• 8: Palma, J.; Mello, A.; Möller, L.; Moraes, F.; Calazans, N. "Core Communication Interface for FPGAs". In: SBCCI'02, pp. 183--188.
• 9: Lim, D.; Peattie, M. "Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations". Xilinx Application Note 290 (v1.0), 2002.
• 10: Huebner, M.; Becker, T.; Becker, J. "Real-Time LUT-Based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration". In: SBCCI'04, pp. 28--32.
• 11: Xilinx, Inc. "MicroBlaze Processor Reference Guide". Reference Guide v4.0 edition, Aug. 2004, 132 pages.
• 12: Moraes, F. et al. "Hermes: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip". Integration, the VLSI Journal, v.38(1), 2004, pp. 69--93.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware; VLSI (very large scale integration)

General Terms:
Design, Experimentation, Measurement, Performance, Theory, Verification

Keywords:
NoCs, configuration controllers, reconfigurable architectures