Bias circuit design for low-voltage cascode transistors

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Bias circuit design for low-voltage cascode transistors

Full text

Pdf (107 KB)

Source

SBCCI archive
Proceedings of the 19th annual symposium on Integrated circuits and systems design table of contents

Ouro Preto, MG, Brazil

SESSION: Analog and mixed signal design table of contents

Pages: 94 - 97

Year of Publication: 2006

ISBN:1-59593-479-0

Authors

Pablo Aguirre	Universidad de la República, Montevideo, Uruguay
Fernando Silveira	Universidad de la República, Montevideo, Uruguay

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): , Downloads (12 Months): , Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1150343.1150372 What is a DOI?

ABSTRACT

This article presents a design methodology for the most simple cascode transistor's bias circuit, i.e. a diode-connected transistor, valid from weak to strong inversion. By taking advantage of a compact MOS transistor model, we show how the circuit can be easily designed to precisely fix the drain voltage of the cascoded transistor just above its saturation voltage. Test circuits were manufactured in a 0.35μm CMOS technology in order to test the design methodology under different operation regions (weak, moderate and strong inversion) and for long and short channel transistors. Standard deviation in measured drain voltage of the cascoded transistor is below 3% of its mean.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	V. Vincence, C. Galup-Montoro, and M. Schneider, "A high-swing MOS cascode bias circuit for operation at any current level," in Proc. Int. Symp. on Circuits and Systems (ISCAS), vol. V, May 2000, pp. 489--492.
	2	P. Heim and M. Jabri, "MOS cascode-mirror biasing circui operating at any current level with minimal output saturation voltage," Electronics Letters, vol. 31, no. 9, pp. 690--691, Apr. 1995.
	3	B. Minch, "A low-voltage MOS cascode bias circuit for al current levels," in Proc. Int. Symp. on Circuits and Systems (ISCAS), vol. III, May 2002, pp. 619--622.
	4	C. Galup-Montoro, M. Schneider, and A. Cunha, "A current-based MOSFET model for integrated circuit design," in Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits, E. Sanchez-Sinencio and A. Andreou, Eds. IEEE Press, ISBN 0-7803-3446-9, 1999, ch. 2, pp. 7--55.
	5	A. Arnaud, R. Fiorelli, and C. Galup-Montoro, "On the design of very small transconductance otas with reduced input offset," in Proc. XVIII Symposium on Integrated Circuits and Systems Design, (SBCCI), Florianopolis, Brasil, Sept. 2005, pp. 15--20.