ByZFAD: a low switching activity architecture for shift-and-add multipliers

ABSTRACT

In this paper, a low-power architecture (ByZFAD Stands for Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications include the removal of the shift of B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of the binary counter, and removal of the partial product shift. To show the efficiency of the architecture, we have compared the switching activity of the proposed architecture with that of the conventional architecture for a radix-2 shift-and-add multiplier. The results for a 32-bit multiplier show that, the proposed architecture lowers the total switching activity up to 76% when compared to the traditional architecture.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles

General Terms:
Algorithms, Design

Keywords:
adder bypass, byZFAD, hot-block ring counter, low-power, shiftand-add multiplier, switching activity