A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

ABSTRACT

We have reported previously [1] a low-swing latch (LSL) with superior performance-power tradeoff compared to the conventional pass-gate master-slave latch. In this paper, hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system power in high-frequency microprocessors. We have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle between two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system power saving can be achieved in pulsed mode compared to non-pulsed mode. Power contribution from individual components is also presented.

REFERENCES

• 1: Pong-Fei Lu et al., IEEE Int SOI Conference, pp. 165--167, 2004.
• 2: Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor Zyuban , Philip N. Strenski , Philip G. Emma, Optimizing pipelines for power and performance, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 3: J. Clabes et al., Techical Digest of ISSCC 2004, p. 56.
• 4: B. Curran, Technical Digest of ISSCC 2001, p. 238.
• 5: D. W. Dobberpuhl et al, IEEE JSSC, Vol. 27, No. 11, pp. 1555--1567 (1992)
• 6: N. Nedovic et al., Integrated Circuits and System Design, pp. 211--215 (2000)
• 7: R. Krishnamurpthy et al., 2002 Symposium on VLSI Circuits, p. 128.
• 8: M. Tokumasu et al., Proceedings of CICC, pp. 129--132, (2002)
• 9: J. D. Warnock & D. Wendle, U.S. Patent 6,822,500 B1 (Nov. 23, 2004)
• 10: B. Curran et al., Technical Digest of ISSCC 2006, p. 436
• 11: S H Unger , Chung-Jen Tan, Clocking schemes for high-speed digital systems, IEEE Transactions on Computers, v.35 n.10, p.880-895, Oct. 1986 [doi>10.1109/TC.1986.1676679]
• 12: V.G. Oklobdzija, IBM J. Res & Dev. 47(5/6) Sept./Nov. 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

General Terms:
Design

Keywords:
latch, low-power, pulse latch