ACM Home Page
Please provide us with feedback. Feedback
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Full text PdfPdf (934 KB)
Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2006 international symposium on Low power electronics and design table of contents
Tegernsee, Bavaria, Germany
SESSION: Thermal and energy aware design table of contents
Pages: 156 - 161  
Year of Publication: 2006
ISBN:1-59593-462-6
Authors
Hao Yu  University of California, Los Angeles, CA
Yiyu Shi  University of California, Los Angeles, CA
Lei He  University of California, Los Angeles, CA
Tanay Karnik  Intel Labs, Hillsboro, OR
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 43,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1165573.1165611
What is a DOI?

ABSTRACT

All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering temporally and spatially variant thermal-power. The transient temperature is calculated using macromodel by a structured and parameterized model reduction, which generates temperature sensitivity with respect to thermal-via density. By defining a thermal-violation integral based on the transient temperature, a nonlinear optimization problem is formulated to allocate thermal-vias and minimize thermal violation integral. This optimization problem is transformed into a sequence of subproblems by Lagrangian relaxation, and each subproblem is solved by quadratic programming using sensitives from the macromodel. Experiments show that compared to the existing method using steady-state thermal analysis, our method is 126X faster to obtain the temperature profile, and reduces the number of thermal vias by 2.04X under the same temperature bound.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration," Proc. IEEE, pp. 602--633, 2001.
 
2
 
3
C. C. Teng, Y. K. Cheng, E. Rosenbaum, and S. M. Kang, "iTEM: A temperature-dependent electromigration reliability diagnosis tool," IEEE Trans. on CAD, pp. 882--893, 1997.
4
5
6
 
7
M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, and S. Velusamy, "Hotspot: a dynamic compact thermal model at the processor-architecture level," Microelectronics Journal, pp. 1153--1165, 2003.
8
 
9
 
10
A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macro-modeling algorithm," IEEE Trans. on CAD, pp. 645--654, 1998.
 
11
L. Daniel, O. C. Siong, L. S. Chay, K. H. Lee, and J. White, "A multiparameter moment matching model reduction approach for generating geometrically parameterized interconnect performance models," IEEE Trans. on CAD, pp. 678--693, 2004.
 
12
 
13
E.J.Grimme, Krylov projection methods for model reduction (Ph. D Thesis). Univ. of Illinois at Urbana-Champaign, 1997.
 
14
C. Visweswariah, R. A. Haring, and A. R. Conn, "Noise considerations in circuit optimization," IEEE Trans. on CAD, pp. 679--690, 2000.
 
15
M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms. John Wiley and Sons, 1993.

Collaborative Colleagues:
Hao Yu: colleagues
Yiyu Shi: colleagues
Lei He: colleagues
Tanay Karnik: colleagues