| Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2006 international symposium on Low power electronics and design
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Tegernsee, Bavaria, Germany
SESSION: Thermal and energy aware design
table of contents
Pages: 156 - 161
Year of Publication: 2006
ISBN:1-59593-462-6
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Authors
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Hao Yu
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University of California, Los Angeles, CA
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Yiyu Shi
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University of California, Los Angeles, CA
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Lei He
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University of California, Los Angeles, CA
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Tanay Karnik
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Intel Labs, Hillsboro, OR
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Downloads (6 Weeks): 5, Downloads (12 Months): 43, Citation Count: 0
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ABSTRACT
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering temporally and spatially variant thermal-power. The transient temperature is calculated using macromodel by a structured and parameterized model reduction, which generates temperature sensitivity with respect to thermal-via density. By defining a thermal-violation integral based on the transient temperature, a nonlinear optimization problem is formulated to allocate thermal-vias and minimize thermal violation integral. This optimization problem is transformed into a sequence of subproblems by Lagrangian relaxation, and each subproblem is solved by quadratic programming using sensitives from the macromodel. Experiments show that compared to the existing method using steady-state thermal analysis, our method is 126X faster to obtain the temperature profile, and reduces the number of thermal vias by 2.04X under the same temperature bound.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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