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Recording shared memory dependencies using strata
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Source Architectural Support for Programming Languages and Operating Systems archive
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems table of contents
San Jose, California, USA
SESSION: Races and memory debugging II table of contents
Pages: 229 - 240  
Year of Publication: 2006
ISBN:1-59593-451-0
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Authors
Satish Narayanasamy  University of California - San Diego
Cristiano Pereira  University of California - San Diego
Brad Calder  Microsoft
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGOPS: ACM Special Interest Group on Operating Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

Significant time is spent by companies trying to reproduce and fix bugs. BugNet and FDR are recent architecture proposals that provide architecture support for deterministic replay debugging. They focus on continuously recording information about the program's execution, which can be communicated back to the developer. Using that information, the developer can deterministically replay the program's execution to reproduce and fix the bugs.In this paper, we propose using Strata to efficiently capture the shared memory dependencies. A stratum creates a time layer across all the logs for the running threads, which separates all the memory operations executed before and after the stratum. A strata log allows us to determine all the shared memory dependencies during replay and thereby supports deterministic replay debugging for multi-threaded programs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M. Prvulovic. Cord: Cost-effective (and nearly overhead-free) orderrecording and data race detection. In International Symposium on High-Performance Computer Architecture, Feb 2005.
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S. Sethumadhavan, R. Desikan, D. Burger, C.R. Moore, and S.W. Kecler. Scalable hardware memory disambiguation for high ilp processors. In International Symposium on Microarchitecture, 2004.
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Collaborative Colleagues:
Satish Narayanasamy: colleagues
Cristiano Pereira: colleagues
Brad Calder: colleagues