Article

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Authors:

Roshan G. Ragel,

Sri ParameswaranAuthors Info & Claims

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Pages 100 - 105

https://doi.org/10.1145/1176254.1176280

Published: 22 October 2006 Publication History

Abstract

Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software-only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted.

References

[1]

Z. Alkhalifa et al. Design and evaluation of system-level checks for on-line control flow error detection. IEEE Transaction on Parallel and Distributed Systems, pages 627--641, 1999.

Digital Library

[2]

S. Bagchi et al. Hierarchical error detection in a software implemented fault tolerance (sift) environment. IEEE Transactions on Knowledge and Data Engineering, 12:203--224, March/April 2000.

Digital Library

[3]

X. Delord and G. Saucier. Control flow checking in pipelined RISC microprocessors: the Motorola MC88100 case study. In EUROMICRO '90, pages 162--169, June 1990.

[4]

X. Delord and G. Saucier. Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors. In Test conference, pages 936--945, October 1991.

Digital Library

[5]

B. Eschermann. On combining off-line BIST and on-line control flow checking. In FTCS -22, pages 298--305, July 1992.

[6]

J. A. Fisher. Customized instruction-sets for embedded processors. In DAC '99, pages 253--257, 1999.

Digital Library

[7]

J. A. Fisher, P. Faraboschi, and G. Desoli. Custom-fit processors: letting applications define architectures. In MICRO 29, pages 324--335, 1996.

Digital Library

[8]

J. Gaisler. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications. In FTCS '94, pages 128--130, 1994.

[9]

O. Goloubeva et al. Soft-error detection using control flow assertions. In DFT '03, pages 581--588, November 2003.

Digital Library

[10]

O. Goloubeva et al. Improved software-based processor control-flow errors detection technique. In Reliability and maintainability symposium, pages 583--589, January 2005.

[11]

M. R. Guthaus et al. Mibench: A free, commercially representative Embedded Benchmark Suite. IEEE 4th Annual Workshop on Workload Characterization, pages 83--94, December 2001.

Digital Library

[12]

G. Kanawati et al. Evaluation of integrated system-level checks for on-line error detection. In Computer performance and dependability symposium, pages 292--301, September 1996.

Digital Library

[13]

R. Leveugle, T. Michel, and G. Saucier. Design of Microprocessors with Built-in On-line Test. In FTCS-20, pages 450--456, June 1990.

[14]

D. J. Lu. Watchdog processors and structural integrity checking. IEEE Trans. Computers, 31(7):681--685, 1982.

Digital Library

[15]

M. R. Lyu, editor. Software Fault Tolerance. John Wiley and Sons Ltd, 1995.

Digital Library

[16]

H. Madeira and J. Silva. On-line signature learning and checking: experimental evaluation. In COMPEURO '91, pages 642--643, July 1991.

[17]

A. Mahmood and E. J. McCluskey. Concurrent error detection using watchdog processors - a survey. IEEE Trans. Computers, 37(2):160--174, 1988.

Digital Library

[18]

L. McFearin and V. Nair. Control-flow checking using assertions. In DCCA '5, pages 103--112. IEEE Computer Society Press, September 1995.

[19]

T. Michel, R. Leveugle, and G. Saucier. A new approach to control flow checking without program modification. In FTCS 21, pages 334--341, 1991.

[20]

T. Michel et al. An application specific microprocessor with two-level built-in control flow checking capabilities. In EURO ASIC '92, pages 310--313, 1992.

[21]

G. Miremadi et al. Two software techniques for on-line error detection. In FTCS 22, pages 328--335, July 1992.

[22]

G. Miremadi et al. Use of time and address signatures for control flow checking. In DCCS '5, pages 201--221, September 1995.

[23]

V. S. S. Nair et al. Design and evaluation of automated high-level checks for signal processing applications. In spie advanced algorithms and architectures for signal processing conference, pages 292--301, August 1996.

[24]

M. Namjoo. Techniques for concurrent testing of vlsi processor operation. Test Conference, pages 461--468, 1982.

[25]

J. Ohlsson and M. Rimen. Implicit signature checking. In FTCS '25, pages 218--227, 1995.

Digital Library

[26]

J. Ohlsson, M. Rimen, and U. Gunneflo. A study of the effects of transient fault injection into a 32-bit risc with built-in watchdog. In FTCS '22, pages 316--325, 1992.

[27]

J. Peddersen et al. Rapid Embedded Hardware/Software System Generation. In In VLSID '05, pages 111--116, 2005.

Digital Library

[28]

B. Ramamurthy and S. Upadhyaya. Watchdog processor-assisted fast recovery in distributed systems. In Fifth Dependable computing for critical applications, pages 125--134, 1995.

[29]

T. Rao. Error coding for arithmetic processors. 1974.

Digital Library

[30]

N. Saxena and E. McCluskey. Control-flow checking using watchdog assists and extended-precision checksums. IEEE Transactions on Computers, pages 554--558, 1990.

Digital Library

[31]

M. Schuette and J. Shen. Processor control flow monitoring using signatured instruction streams. IEEE Trans. Computers, pages 264--276, March 1987.

Digital Library

[32]

M. A. Schuette et al. Experimental evaluation of two concurrent error detection schemes. In FTCS '16, pages 138--143, July 1986.

[33]

J. Sosnowski. Detection of control flow errors using signature and checking instructions. IEEE International Test Conference, pages 81--88, 1988.

[34]

The PEAS Team. ASIP Meister, Available at http://www.eda-meister.org/asip-meister/, 2002.

[35]

S. Upadhyaya and B. Ramamurthy. Concurrent process monitoring with no reference signatures. IEEE Transactions on Computers, 43:475--480, April 1994.

Digital Library

[36]

K. Wilken and J. Shen. Continuous signature monitoring: low-cost concurrent detection of processor control errors. Computer-Aided Design of Integrated Circuits and Systems, pages 629--641, June 1990.

Digital Library

[37]

S. S. Yau and F. Chen. An approach to concurrent control flow checking. IEEE Trans. Software Eng., 6(2):126--137, 1980.

Digital Library

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Zhang ZPark SMahlke SXue JJung C(2020)Path Sensitive Signatures for Control Flow Error DetectionThe 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3372799.3394360(62-73)Online publication date: 16-Jun-2020
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Index Terms

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Conferences

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

October 2006

328 pages

ISBN:1595933700

DOI:10.1145/1176254

General Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center, USA
,
Program Chair:
Kiyoung Choi
Seoul National University, Korea

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 October 2006

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ESWEEK06

Sponsor:

ESWEEK06: Second Embedded Systems Week 2006

October 22 - 25, 2006

Seoul, Korea

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Dehghani MElahi MFazeli MPatooghy A(2024)Advancing IoT Security Through Run-time Monitoring & Post-Execution Verification2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00164(825-829)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00164
Zhang ZPark SMahlke SXue JJung C(2020)Path Sensitive Signatures for Control Flow Error DetectionThe 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3372799.3394360(62-73)Online publication date: 16-Jun-2020
https://dl.acm.org/doi/10.1145/3372799.3394360
Rajabpour NSedaghat Y(2015)A hybrid-based error detection technique for PLC-based Industrial Control Systems2015 IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA)10.1109/ETFA.2015.7301525(1-7)Online publication date: Sep-2015
https://doi.org/10.1109/ETFA.2015.7301525
Wang HWang HJin Z(2015)Bipartite graph-based control flow checking for COTS-based small satellitesChinese Journal of Aeronautics10.1016/j.cja.2015.04.01028:3(883-893)Online publication date: Jun-2015
https://doi.org/10.1016/j.cja.2015.04.010
Rajabpour NSedaghat Y(2015)A Software-Based Error Detection Technique for Monitoring the Program Execution of RTUs in SCADAProceedings of the 34th International Conference on Computer Safety, Reliability, and Security - Volume 933710.1007/978-3-319-24255-2_33(457-470)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1007/978-3-319-24255-2_33
Christoforakis ITomoutzoglou OBakoyiannis DKornaros G(2014)Runtime Adaptation of Embedded Tasks with A-Priori Known Timing Behavior Utilizing On-Line Partner-Core Monitoring and RecoveryProceedings of the 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2014.10(1-8)Online publication date: 26-Aug-2014
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Santos JFei Y(2013)Leveraging speculative architectures for runtime program validationACM Transactions on Embedded Computing Systems10.1145/251245613:1(1-18)Online publication date: 5-Sep-2013
https://dl.acm.org/doi/10.1145/2512456
Punt MTomasevic MDjordjevic J(2013)Evaluation and analysis of an on-line error detection monitoring techniqueComputers and Electrical Engineering10.1016/j.compeleceng.2012.11.01139:2(261-273)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1016/j.compeleceng.2012.11.011
Seepers RStrydis CGaydadjiev G(2012)Architecture-level fault-tolerance for biomedical implants2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404163(104-112)Online publication date: Jul-2012
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Abdur Rouf MKim S(2012)Low-cost control flow error protection by exploiting available redundancies in the pipeline17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164941(175-180)Online publication date: Jan-2012
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