Article

Heterogeneous multiprocessor implementations for JPEG:: a case study

Authors:

Sri ParameswaranAuthors Info & Claims

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Pages 217 - 222

https://doi.org/10.1145/1176254.1176307

Published: 22 October 2006 Publication History

Abstract

Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we explore the use of multiple cores to speed up the JPEG compression algorithm. We show two methods to parallelize this algorithm: one, a master-slave model; and two, a pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues. We show that even with this relatively simple application, parallelization can be carried out with up to nine processors with utilization of between 50% to 80%. We obtained speed ups of up to 4.6X with a seven core system with an area increase of 3.1X.

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Cited By

Gunawardana KAdhikari CNawinne I(2024)Optimized Multi-Processor System-on-Chip (MPSoC) Design for Low-Resource JPEG Encoding2024 6th International Conference on Advancements in Computing (ICAC)10.1109/ICAC64487.2024.10851123(115-120)Online publication date: 12-Dec-2024
https://doi.org/10.1109/ICAC64487.2024.10851123
Usama Iqbal MGul Khawaja SKhan SShaukat A(2022)Framework for Dynamic Partial Configuration of Algorithms for Zynq-7000 SoC using JPEG as Case Study2022 2nd International Conference on Digital Futures and Transformative Technologies (ICoDT2)10.1109/ICoDT255437.2022.9787460(1-8)Online publication date: 24-May-2022
https://doi.org/10.1109/ICoDT255437.2022.9787460
Gnanasambandapillai VPeddersen JRagel RParameswaran S(2020)FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012211(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012211
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Index Terms

Heterogeneous multiprocessor implementations for JPEG:: a case study
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. General and reference
  1. Cross-computing tools and techniques
    1. Design

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Published In

cover image ACM Conferences

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

October 2006

328 pages

ISBN:1595933700

DOI:10.1145/1176254

General Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center, USA
,
Program Chair:
Kiyoung Choi
Seoul National University, Korea

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 October 2006

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ESWEEK06

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ESWEEK06: Second Embedded Systems Week 2006

October 22 - 25, 2006

Seoul, Korea

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Gunawardana KAdhikari CNawinne I(2024)Optimized Multi-Processor System-on-Chip (MPSoC) Design for Low-Resource JPEG Encoding2024 6th International Conference on Advancements in Computing (ICAC)10.1109/ICAC64487.2024.10851123(115-120)Online publication date: 12-Dec-2024
https://doi.org/10.1109/ICAC64487.2024.10851123
Usama Iqbal MGul Khawaja SKhan SShaukat A(2022)Framework for Dynamic Partial Configuration of Algorithms for Zynq-7000 SoC using JPEG as Case Study2022 2nd International Conference on Digital Futures and Transformative Technologies (ICoDT2)10.1109/ICoDT255437.2022.9787460(1-8)Online publication date: 24-May-2022
https://doi.org/10.1109/ICoDT255437.2022.9787460
Gnanasambandapillai VPeddersen JRagel RParameswaran S(2020)FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012211(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012211
Chen GHuang KBuckl CKnoll A(2015)Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor SystemsACM Transactions on Design Automation of Electronic Systems10.1145/269986520:2(1-27)Online publication date: 2-Mar-2015
https://dl.acm.org/doi/10.1145/2699865
Javaid HIgnjatovic AParameswaran S(2014)Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)IEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.26825:8(2159-2168)Online publication date: Aug-2014
https://doi.org/10.1109/TPDS.2013.268
Chen GHuang KKnoll A(2014)Adaptive dynamic power management for hard real-time pipelined Multiprocessor Systems2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2014.6910525(1-10)Online publication date: Aug-2014
https://doi.org/10.1109/RTCSA.2014.6910525
Kim KGajski D(2014)Hierarchy-Aware mapping of pipelined applications2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2014.6908494(631-634)Online publication date: Aug-2014
https://doi.org/10.1109/MWSCAS.2014.6908494
Ozturk OTosun SJeannot EŽilinskas J(2014)Enabling Network Security in HPC Systems Using Heterogeneous CMPsHigh‐Performance Computing on Complex Environments10.1002/9781118711897.ch20(383-399)Online publication date: 18-Apr-2014
https://doi.org/10.1002/9781118711897.ch20
Bathen LAhn YPasricha SDutt N(2013)MultiMaKeACM Transactions on Embedded Computing Systems10.1145/2435227.243525512:1s(1-25)Online publication date: 29-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435255
Muthukaruppan TJavaid HMitra TParameswaran S(2013)Energy-aware synthesis of application specific MPSoCs2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657026(62-69)Online publication date: Oct-2013
https://doi.org/10.1109/ICCD.2013.6657026
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