A flexible data to L2 cache mapping approach for future multicore processors

ABSTRACT

This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for high program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied "pure" hardware-based private and shared cache designs, the proposed OS-microarchitecture approach allows mimicking a wide spectrum of L2 caching policies without complex hardware support. Moreover, processors and cache slices can be isolated from each other without hardware modifications, resulting in improved chip reliability characteristics. We discuss the key design issues and implementation strategies of the proposed approach, and present an experimental result showing the promise of it.

REFERENCES

• 1: Todd Austin , Eric Larson , Dan Ernst, SimpleScalar: An Infrastructure for Computer System Modeling, Computer, v.35 n.2, p.59-67, February 2002 [doi>10.1109/2.982917 ]
• 2: Maurice J. Bach, The design of the UNIX operating system, Prentice-Hall, Inc., Upper Saddle River, NJ, 1986
• 3: S. Borkar et al. "Platform 2015: Intel Processor and Platform Evolution for the Next Decade," Technology@Intel Magazine, March 2005.
• 4: Doug Burger , James R. Goodman, Billion-Transistor Architectures: There and Back Again, Computer, v.37 n.3, p.22-28, March 2004 [doi>10.1109/MC.2004.1273999]
• 5: Jichuan Chang , Gurindar S. Sohi, Cooperative Caching for Chip Multiprocessors, Proceedings of the 33rd annual international symposium on Computer Architecture, p.264-276, June 17-21, 2006
• 6: Zeshan Chishti , Michael D. Powell , T. N. Vijaykumar, Optimizing Replication, Communication, and Capacity Allocation in CMPs, Proceedings of the 32nd Annual International Symposium on Computer Architecture, p.357-368, June 04-08, 2005
• 7: Jaehyuk Huh , Doug Burger , Stephen W. Keckler, Exploring the Design Space of Future CMPs, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.199-210, September 08-12, 2001
• 8: Jaehyuk Huh , Changkyu Kim , Hazim Shafi , Lixin Zhang , Doug Burger , Stephen W. Keckler, A NUCA substrate for flexible CMP cache sharing, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts [doi>10.1145/1088149.1088154]
• 9: Intel Corp. "A New Era of Architectural Innovation Arrives with Intel Dual-Core Processors," Technology@Intel Magazine, May 2005.
• 10: ITRS (Int'l Technology Roadmap for Semiconductors). 2005 Edition, http://public.itrs.net.
• 11: Ravi Iyer, CQoS: a framework for enabling QoS in shared caches of CMP platforms, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France [doi>10.1145/1006209.1006246]
• 12: A. Jaleel, M. Mattina, and B. Jacob. "Last Level Cache (LLC) Performance of Data Mining Workloads on a CMP - A Case Study of Parallel Bioinformatics Workloads," Proc. Int'l Symp. High-Perf. Computer Arch., pp. 88--98, Feb. 2006.
• 13: R. E. Kessler , Mark D. Hill, Page placement algorithms for large real-indexed caches, ACM Transactions on Computer Systems (TOCS), v.10 n.4, p.338-359, Nov. 1992 [doi>10.1145/138873.138876]
• 14: Changkyu Kim , Doug Burger , Stephen W. Keckler, An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 15: Jinseok Kong , Gyungho Lee, Relaxing the Inclusion Property in Cache Only Memory Architecture, Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II, p.435-444, August 26-29, 1996
• 16: Poonacha Kongetira , Kathirgamar Aingaran , Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, v.25 n.2, p.21-29, March 2005 [doi>10.1109/MM.2005.35]
• 17: Chun Liu , Anand Sivasubramaniam , Mahmut Kandemir, Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs, Proceedings of the 10th International Symposium on High Performance Computer Architecture, p.176, February 14-18, 2004 [doi>10.1109/HPCA.2004.10017]
• 18: B. A. Nayfeh , K. Olukotun, Exploring the design space for a shared-cache multiprocessor, Proceedings of the 21ST annual international symposium on Computer architecture, p.166-175, April 18-21, 1994, Chicago, Illinois, United States
• 19: B. A. Nayfeh , K. Olukotun , J. P. Singh, The impact of shared-cache clustering in small-scale shared-memory multiprocessors, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.74, February 03-07, 1996
• 20: Timothy Sherwood , Brad Calder , Joel Emer, Reducing cache misses using hardware and software page placement, Proceedings of the 13th international conference on Supercomputing, p.155-164, June 20-25, 1999, Rhodes, Greece [doi>10.1145/305138.305189]
• 21: B. Sinharoy , R. N. Kalla , J. M. Tendler , R. J. Eickemeyer , J. B. Joyner, POWER5 System microarchitecture, IBM Journal of Research and Development, v.49 n.4/5, p.505-521, July 2005
• 22: Evan Speight , Hazim Shafi , Lixin Zhang , Ram Rajamony, Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors, Proceedings of the 32nd Annual International Symposium on Computer Architecture, p.346-356, June 04-08, 2005
• 23: Jayanth Srinivasan , Sarita V. Adve , Pradip Bose , Jude A. Rivers, The Impact of Technology Scaling on Lifetime Reliability, Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN'04), p.177, June 28-July 01, 2004
• 24: Standard Performance Evaluation Corporation. http://www.specbench.org.
• 25: Steven Cameron Woo , Moriyoshi Ohara , Evan Torrie , Jaswinder Pal Singh , Anoop Gupta, The SPLASH-2 programs: characterization and methodological considerations, Proceedings of the 22nd annual international symposium on Computer architecture, p.24-36, June 22-24, 1995, S. Margherita Ligure, Italy
• 26: Michael Zhang , Krste Asanovic, Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors, Proceedings of the 32nd Annual International Symposium on Computer Architecture, p.336-345, June 04-08, 2005

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures

Additional Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.2 Storage Management

General Terms:
Design, Management, Performance

Keywords:
non-uniform cache architecture (NUCA), page allocation