Article

Design of a logic element for implementing an asynchronous FPGA

Author:

Scott C. SmithAuthors Info & Claims

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Pages 13 - 22

https://doi.org/10.1145/1216919.1216922

Published: 18 February 2007 Publication History

Abstract

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

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Cited By

Yu JBeckett PCavallaro JZhang TJones ALi H(2014)A dual-rail LUT for reconfigurable logic using null convention logicProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591589(261-266)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591589
Sui BFang LZhang C(2011)Reconfigurable logic based on tunable periodic characteristics of single-electron transistor2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)10.1109/CCECE.2011.6030497(000485-000488)Online publication date: May-2011
https://doi.org/10.1109/CCECE.2011.6030497

Index Terms

Design of a logic element for implementing an asynchronous FPGA
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits

Two versions of a reconfigurable logic element are developed for use in constructing a NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. ...
Design and characterization of NULL convention arithmetic logic units

In this paper, a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delay-insensitive NULL convention logic paradigm, and are characterized in terms of speed and area. Both dual-rail and quad-rail, pipelined and non-...
Optimization of NULL convention self-timed circuits

Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of ...

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Published In

cover image ACM Conferences

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

February 2007

248 pages

ISBN:9781595936004

DOI:10.1145/1216919

General Chair:
André DeHon
University of Pennsylvania, USA
,
Program Chair:
Mike Hutton
Altera, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 February 2007

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FPGA07

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FPGA07: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2007

February 18 - 20, 2007

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Yu JBeckett PCavallaro JZhang TJones ALi H(2014)A dual-rail LUT for reconfigurable logic using null convention logicProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591589(261-266)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591589
Sui BFang LZhang C(2011)Reconfigurable logic based on tunable periodic characteristics of single-electron transistor2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)10.1109/CCECE.2011.6030497(000485-000488)Online publication date: May-2011
https://doi.org/10.1109/CCECE.2011.6030497

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