Article

Variation-aware routing for FPGAs

Authors:

Satish Sivaswamy,

Kia BazarganAuthors Info & Claims

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Pages 71 - 79

https://doi.org/10.1145/1216919.1216930

Published: 18 February 2007 Publication History

Abstract

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks.

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Cited By

Wei SZheng JPotkonjak MHutchings BBetz V(2013)Low power FPGA design using post-silicon device aging (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435340(277-277)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435340
Mehta NRubin RDeHon ACompton KHutchings B(2012)Limit study of energy & delay benefits of component-specific routingProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145710(97-106)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145710
Yu HXu QLeong P(2011)On Timing Yield Improvement for FPGA Designs Using Architectural SymmetryProceedings of the 2011 21st International Conference on Field Programmable Logic and Applications10.1109/FPL.2011.105(539-544)Online publication date: 5-Sep-2011
https://dl.acm.org/doi/10.1109/FPL.2011.105
Show More Cited By

Index Terms

Variation-aware routing for FPGAs
1. Hardware
  1. Integrated circuits
  2. Robustness

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Published In

cover image ACM Conferences

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

February 2007

248 pages

ISBN:9781595936004

DOI:10.1145/1216919

General Chair:
André DeHon
University of Pennsylvania, USA
,
Program Chair:
Mike Hutton
Altera, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 February 2007

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FPGA07

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FPGA07: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2007

February 18 - 20, 2007

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Wei SZheng JPotkonjak MHutchings BBetz V(2013)Low power FPGA design using post-silicon device aging (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435340(277-277)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435340
Mehta NRubin RDeHon ACompton KHutchings B(2012)Limit study of energy & delay benefits of component-specific routingProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145710(97-106)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145710
Yu HXu QLeong P(2011)On Timing Yield Improvement for FPGA Designs Using Architectural SymmetryProceedings of the 2011 21st International Conference on Field Programmable Logic and Applications10.1109/FPL.2011.105(539-544)Online publication date: 5-Sep-2011
https://dl.acm.org/doi/10.1109/FPL.2011.105
Aghamirzaie DRazavi SSaheb Zamani MNabiyouni M(2010)Reduction of process variation effect on FPGAs using multiple configurations2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip10.1109/VLSISOC.2010.5642616(85-90)Online publication date: Sep-2010
https://doi.org/10.1109/VLSISOC.2010.5642616
Kumar AAnis M(2010)FPGA design for timing yield under process variationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201155518:3(423-435)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011555
Yu HXu QLeong P(2010)Fine-grained characterization of process variation in FPGAs2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681770(138-145)Online publication date: Dec-2010
https://doi.org/10.1109/FPT.2010.5681770
Kumar AAnis M(2010)Robust FPGA Design under VariationsProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.60(259-262)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.1109/FPL.2010.60
Dong CChilstedt SChen D(2010)FPCNA: A Carbon Nanotube-Based Programmable ArchitectureNanoelectronic Circuit Design10.1007/978-1-4419-7609-3_9(307-348)Online publication date: 19-Nov-2010
https://doi.org/10.1007/978-1-4419-7609-3_9
Dong CChilstedt SChen DChow PCheung P(2009)FPCNAProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508154(161-170)Online publication date: 24-Feb-2009
https://dl.acm.org/doi/10.1145/1508128.1508154
Dong CChilstedt SChen D(2009)Variation Aware Routing for Three-Dimensional FPGAsProceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2009.44(298-303)Online publication date: 13-May-2009
https://dl.acm.org/doi/10.1109/ISVLSI.2009.44
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