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Simulation analysis on the impact of furnace batch size increase in a deposition loop

Published: 03 December 2006 Publication History

Abstract

In the dynamic environment of semiconductor manufacturing operations, a bottleneck could be created at the bake furnaces of the deposition loop as capacity expands. Upgrading of the bake furnaces by adding a lot-per-batch in the boat or purchasing a new furnace are two possible solutions to this problem. A simulation model was constructed to assist the decision making, with the behavior of the wet benches (upstream tools) and cluster tools (downstream tools) being modeled in detail. We concluded that a limited number of furnaces upgrade is sufficient to sustain the capacity expansion. But the bottleneck was shifted to an upstream tool, which required the backup tool to be activated to manage the queue. A loading policy that constrains batches to queue at maximum time before loading into the furnaces has to be implemented to balance the efficiency at the furnaces and their downstream tools, without compromising on the cycle time.

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Cited By

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  • (2015)Sequencing optimisation for makespan improvement at wet-etch toolsComputers and Operations Research10.1016/j.cor.2014.04.01653:C(261-274)Online publication date: 1-Jan-2015
  • (2012)Using simulation and hybrid sequencing optimization for makespan reduction at a wet toolProceedings of the Winter Simulation Conference10.5555/2429759.2430018(1-13)Online publication date: 9-Dec-2012
  • (2008)An optimization framework for waferfab performance enhancementProceedings of the 40th Conference on Winter Simulation10.5555/1516744.1517127(2194-2200)Online publication date: 7-Dec-2008
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  1. Simulation analysis on the impact of furnace batch size increase in a deposition loop

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    Published In

    cover image ACM Conferences
    WSC '06: Proceedings of the 38th conference on Winter simulation
    December 2006
    2429 pages
    ISBN:1424405017

    Sponsors

    • IIE: Institute of Industrial Engineers
    • ASA: American Statistical Association
    • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
    • IEEE-CS\DATC: The IEEE Computer Society
    • SIGSIM: ACM Special Interest Group on Simulation and Modeling
    • NIST: National Institute of Standards and Technology
    • (SCS): The Society for Modeling and Simulation International
    • INFORMS-CS: Institute for Operations Research and the Management Sciences-College on Simulation

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    Winter Simulation Conference

    Publication History

    Published: 03 December 2006

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    WSC06
    Sponsor:
    • IIE
    • ASA
    • IEICE ESS
    • IEEE-CS\DATC
    • SIGSIM
    • NIST
    • (SCS)
    • INFORMS-CS
    WSC06: Winter Simulation Conference 2006
    December 3 - 6, 2006
    California, Monterey

    Acceptance Rates

    WSC '06 Paper Acceptance Rate 177 of 252 submissions, 70%;
    Overall Acceptance Rate 3,413 of 5,075 submissions, 67%

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    Cited By

    View all
    • (2015)Sequencing optimisation for makespan improvement at wet-etch toolsComputers and Operations Research10.1016/j.cor.2014.04.01653:C(261-274)Online publication date: 1-Jan-2015
    • (2012)Using simulation and hybrid sequencing optimization for makespan reduction at a wet toolProceedings of the Winter Simulation Conference10.5555/2429759.2430018(1-13)Online publication date: 9-Dec-2012
    • (2008)An optimization framework for waferfab performance enhancementProceedings of the 40th Conference on Winter Simulation10.5555/1516744.1517127(2194-2200)Online publication date: 7-Dec-2008
    • (2008)Preventive what-if analysis in symbiotic simulationProceedings of the 40th Conference on Winter Simulation10.5555/1516744.1516883(750-758)Online publication date: 7-Dec-2008

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