An argument against scalable cache coherency

Abstract

Recently there has been considerable interest in cache coherency protocols in shared-memory multiprocessor systems, particularly in protocols which are scalable, i.e. efficient in very large systems. In this position paper, it will be argued that in most multiprocessor applications scalability---or for that matter, systemwide cache coherency itself---is unnecessary, no matter how large the system is. Since even an efficient protocol will be a significant inhibitor of performance, it is then argued that systems not be built with systemwide coherency. Instead, a concept of "local coherency" is proposed. In this approach, though the shared-memory paradigm is retained and the system is still assumed to consist of a very large number of processors, hardware support for accessing shared variables exists only within groups of processors. Accordingly, it is asserted that the main research in cache coherency protocols should concentrate on developing efficient protocols for small and medium numbers of caches rather than on scalability.

References

1. 1. J. Boyle, R. Butler, T. Disz, B. Glickfield, E. Lusk, R. Overbeek, J. Patterson and R. Stevens. Portable Programs for Parallel Processors, 1987, Holt, Rinehart & Winston.
2. 2. D. James, A. Laundrie, S. Gjessing and G. Sohi. "Scalable Coherent Interface," Computer, June 1990, 74-77.
3. 3. N. Matloff. "On Decentralized Task Allocation and Scalable Cache Coherency." Technical Report, Division of Computer Science, University of California at Davis, 1991.
4. 4. L. Ni and C.-F. Wu. "Design Tradeoffs for Process Scheduling in Shared Memory Multiprocessor Systems," IEEE Transactions on Software Engineering, 15, 1989, 327-334.
5. 5. G. Pfister and V. A. Norton. "'Hot Spot' Contention and Combining in Multistage Interconnection Networks," IEEE Transactions on Computers, C-34, 1985, 943-948.
6. 6. P. Stenstrom. "A Survey of Cache Coherency Schemes for Multiprocessors," Computer, June 1990, 12-24.
7. 7. A. Wilson. "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors," Proceedings of the 14th International Symposium on Computer Architecture, 1987, 244-252.
8. 8. P.-C. Yew, N.-F. Tzeng and D. Lawrie. "Distributing Hot-Spot Addressing in Large-Scale Multiprocessors," IEEE Transactions on Computers, C-36, 1987, 388-395.

Index Terms

• Computer systems organization

  • Architectures

    • Parallel architectures

      • Multiple instruction, multiple data

  • Dependable and fault-tolerant systems and networks

• General and reference

  • Cross-computing tools and techniques

    • Performance

• Hardware

  • Integrated circuits

    • Semiconductor memory

      • Dynamic memory

• Networks

  • Network performance evaluation

  • Network protocols