Design challenges in 45nm and below: DFM, low-power and design for reliability

ABSTRACT

Designing in 45nm allows another doubling in transistor density vs 65nm, both for logic gates and for SRAM cells. However, Lithography implications are such that Design rules have to be augmented with recommended rules and regular design, and verified with full Lithography and CMP simulation. Low-power techniques have to be even more elaborate than in 65nm, to compensate for less natural voltage swing in logic and SRAMs, and more gate leakage. Finally, reliability and ESD models have to be taken into account by design and phenomena such as Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are part of library and chip design verification suites. It is only with a holistic approach encompassing process, device modeling, reliability, litho, memory designers, IO designers, power switch experts, that the full capabilities of the 45nm node will be unleashed.

INDEX TERMS

General Terms:
Design

Keywords:
design for manufacturability, design for reliability, low-power design