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Design challenges in 45nm and below: DFM, low-power and design for reliability

Published: 11 March 2007 Publication History

Abstract

Designing in 45nm allows another doubling in transistor density vs 65nm, both for logic gates and for SRAM cells. However, Lithography implications are such that Design rules have to be augmented with recommended rules and regular design, and verified with full Lithography and CMP simulation. Low-power techniques have to be even more elaborate than in 65nm, to compensate for less natural voltage swing in logic and SRAMs, and more gate leakage. Finally, reliability and ESD models have to be taken into account by design and phenomena such as Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are part of library and chip design verification suites. It is only with a holistic approach encompassing process, device modeling, reliability, litho, memory designers, IO designers, power switch experts, that the full capabilities of the 45nm node will be unleashed.
  1. Design challenges in 45nm and below: DFM, low-power and design for reliability

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. design for manufacturability
    2. design for reliability
    3. low-power design

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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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