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Sleep transistor distribution in row-based MTCMOS designs

Published: 11 March 2007 Publication History

Abstract

The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce sub threshold leakage currents during the standby mode of CMOS VLSI Circuits. The performance of MTCMOS circuits strongly depends on the size of the sleep transistors and the parasitics on the virtual ground network. Given a placed net list of a row-based MTCMOS design and the number of sleep transistor cells on each standard cell row, this paper introduces an optimal algorithm for linearly placing the allocated sleep transistors on each standard cell row so as to minimize the performance degradation of the MTCMOS circuit, which is in part due to unwanted voltage drops on its virtual ground network. Experimental results show that, compared to existing methods of placing the sleep transistors on cell rows, the proposed technique results in up to 11% reduction in the critical path delay of the circuit.

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
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    Published: 11 March 2007

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    Author Tags

    1. MTCMOS
    2. leakage minimization
    3. placement

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    March 11 - 13, 2007
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    Cited By

    View all
    • (2013)Early detection of current hot spots in power gated designsProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648681(45-50)Online publication date: 4-Sep-2013
    • (2013)A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assistInternational Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2013.6629266(51-56)Online publication date: Sep-2013
    • (2013)Early detection of current hot spots in power gated designsInternational Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2013.6629265(45-50)Online publication date: Sep-2013
    • (2012)Synthesis of Active-Mode Power-Gating CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217196331:3(391-403)Online publication date: 1-Mar-2012
    • (2010)Synthesis and implementation of active mode power gating circuitsProceedings of the 47th Design Automation Conference10.1145/1837274.1837395(487-492)Online publication date: 13-Jun-2010
    • (2010)Power gatingACM Transactions on Design Automation of Electronic Systems10.1145/1835420.183542115:4(1-37)Online publication date: 7-Oct-2010
    • (2009)A design methodology for high-performance and low-leakage fixed-point transpose FIR filters2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)10.1109/ICECS.2009.5410902(415-418)Online publication date: Dec-2009

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