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An optimized linear skewing interleave scheme for on-chip multi-access memory systems

Published: 11 March 2007 Publication History

Abstract

An optimized linear skewing interleave scheme for on-chip multi-access memory systems is proposed in this paper. The proposed scheme can support simultaneous access of multiple subarray types of data elements in a 2-D data space with modulo addressing. 2pq (pq is the number of data elements in a subarray) memory modules are used without redundancy to save the on-chip memory. It uses linear skewing in the horizontal direction and uses nonlinear skewing in the vertical direction. Fast implementation method for the proposed scheme is also described. Results show that compared to previous linear skewing schemes, the proposed scheme can reduce 13.6%, on average, of the on-chip memory for cases of pq = 4 or 8 and reduce 35.5%, on average, of the external memory bandwidth for benchmark of motion estimation due to modulo addressing.

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Cited By

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  • (2019)Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLSVLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms10.1007/978-3-030-23425-6_4(53-78)Online publication date: 26-Jun-2019
  • (2018)New access modes of parallel memory subsystem for sub-pixel motion estimationJournal of Real-Time Image Processing10.1007/s11554-014-0481-315:2(279-296)Online publication date: 1-Aug-2018
  • (2018)Conflict-Free Block-with-Stride Access of 2D Storage StructureAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-05057-3_46(618-629)Online publication date: 7-Dec-2018
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  1. An optimized linear skewing interleave scheme for on-chip multi-access memory systems

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. interleave scheme
    2. linear skewing
    3. multi-access memory

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    March 11 - 13, 2007
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    View all
    • (2019)Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLSVLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms10.1007/978-3-030-23425-6_4(53-78)Online publication date: 26-Jun-2019
    • (2018)New access modes of parallel memory subsystem for sub-pixel motion estimationJournal of Real-Time Image Processing10.1007/s11554-014-0481-315:2(279-296)Online publication date: 1-Aug-2018
    • (2018)Conflict-Free Block-with-Stride Access of 2D Storage StructureAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-05057-3_46(618-629)Online publication date: 7-Dec-2018
    • (2012)A novel parallel memory organization supporting multiple access types with matched memory modulesIEICE Electronics Express10.1587/elex.9.6029:6(602-608)Online publication date: 2012
    • (2010)A Graphics Parallel Memory Organization Exploiting Request CorrelationsIEEE Transactions on Computers10.1109/TC.2010.4859:6(762-775)Online publication date: 1-Jun-2010
    • (2007)An efficient programmable engine for interpolation of multi-standard video coding2007 7th International Conference on ASIC10.1109/ICASIC.2007.4415739(750-753)Online publication date: Oct-2007

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