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I-cache multi-banking and vertical interleaving

Published: 11 March 2007 Publication History

Abstract

This research investigates the impact of a microarchitectural technique called vertical interleaving in multi-banked caches. Unlike previous multi-banking and interleaving techniques to increase cache bandwidth, the proposed vertical interleaving further divides memory banks in a cache into vertically arranged sub-banks, which are selectively accessed based on the memory address. Under this setting, we are particularly interested in how accesses to instruction cache are dispersed toward different cache banks. We quantitatively analyze the memory access pattern seen by each cache bank and establish the relationship between important cache parameters and the access patterns. Our study shows that the vertical interleaving technique distributes accesses among different banks with tightly bounded run lengths. We then discuss possible applications that utilize the presented concept, including power density reduction. Very simple interleaving configurations can lead to as much as 67% reduction of maximum power density under a realistic machine configuration. Our study suggests that the idea of vertically interleaving cache lines has potential for optimizing memory accesses in a number of interesting ways.

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  • (2018)Fast write operations in non-volatile memories using latency masking2018 Real-Time and Embedded Systems and Technologies (RTEST)10.1109/RTEST.2018.8397072(1-7)Online publication date: May-2018

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 March 2007

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Author Tags

  1. cache memory
  2. memory sub-banking
  3. power density

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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2021)Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded SystemsIEEE Transactions on Computers10.1109/TC.2020.298826170:3(359-371)Online publication date: 1-Mar-2021
  • (2018)Fast write operations in non-volatile memories using latency masking2018 Real-Time and Embedded Systems and Technologies (RTEST)10.1109/RTEST.2018.8397072(1-7)Online publication date: May-2018

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