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A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Published: 11 March 2007 Publication History

Abstract

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18μm technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

References

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Joint Video Team, Draft ITU-T recommendation and final draft international standard of joint video specification, ITU-T Rec. H.264 and ISO/IEC, 14496--10 AVC, May 2003.
[2]
Pan, F., Lin, X., Rahardja, S., Lim, K. P., Li, Z. G., Wu, D. J. and Wu, S. Fast mode decision algorithm for intraprediction in H.264/AVC video coding, IEEE Trans. Circuits Syst. Video Tech., 15, 7, (Jul. 2005), 813--822.
[3]
Liao, N., Quan, Z. Y. and Men, A. D. Enhanced fast mode decision based on edge map and motion detail analysis for H.264/JVT, In Proceedings of the IEEE International Workshop on VLSI Design and Video Technology, (May 2005), 187--190.
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Kalva, H., Petljansk, B. and Furht, B. Complexity reduction tools for MPEG-2 to H.264 video transcoding, WSEAS Trans. Info. Science & Appli., 2, (Mar. 2005), 295--300.
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Jiang, G.Y., Li, S.P., Yu, M. and Li, F.C. An efficient fast mode selection for intra prediction, In Proceedings of the IEEE International Workshop on VLSI Design and Video Technology, (May 2005), 357--360.
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Wang, J.F., Wang, J.C., Chen, J.T., Tsai, A.C. and Paul, A. A novel fast algorithm for intra mode decision in H.264/AVC encoders, In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) (May 2006). 3498--3501.
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JVT Test Model Ad Hoc Group, Evaluation sheet for motion estimation, Draft version 4, Feb. 19, 2003.
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Huang, Y.W., Hsieh, B.Y., Chen, T.C. and Chen, L.G. Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder, IEEE Trans. Circuits Syst. Video Tech., 15, 3, (Mar. 2005), 378--401.
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Cited By

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  • (2018)VLSI design of energy efficient computational centric smart objects for IoT2018 15th Learning and Technology Conference (L&T)10.1109/LT.2018.8368497(129-138)Online publication date: Mar-2018
  • (2013)Iterative intra prediction search for H.265/HEVC2013 International Siberian Conference on Control and Communications (SIBCON)10.1109/SIBCON.2013.6693615(1-4)Online publication date: Sep-2013
  • (2013)Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6571780(53-56)Online publication date: May-2013
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  1. A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      Published: 11 March 2007

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      Author Tags

      1. H.264
      2. VLSI architecture
      3. fast intra prediction mode decision

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      March 11 - 13, 2007
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      Cited By

      View all
      • (2018)VLSI design of energy efficient computational centric smart objects for IoT2018 15th Learning and Technology Conference (L&T)10.1109/LT.2018.8368497(129-138)Online publication date: Mar-2018
      • (2013)Iterative intra prediction search for H.265/HEVC2013 International Siberian Conference on Control and Communications (SIBCON)10.1109/SIBCON.2013.6693615(1-4)Online publication date: Sep-2013
      • (2013)Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6571780(53-56)Online publication date: May-2013
      • (2011)Methodology and technique to improve throughput of FPGA-based Cal dataflow programs: Case study of the RVC MPEG-4 SP Intra decoder2011 IEEE Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2011.6088972(186-191)Online publication date: Oct-2011
      • (2011)A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDAProceedings of the 2011 Sixth International Conference on Image and Graphics10.1109/ICIG.2011.99(76-81)Online publication date: 12-Aug-2011
      • (2010)Understanding sources of inefficiency in general-purpose chipsACM SIGARCH Computer Architecture News10.1145/1816038.181596838:3(37-47)Online publication date: 19-Jun-2010
      • (2010)Understanding sources of inefficiency in general-purpose chipsProceedings of the 37th annual international symposium on Computer architecture10.1145/1815961.1815968(37-47)Online publication date: 19-Jun-2010
      • (2010)Parallel Streaming Intra Prediction for Full HD H.264 Encoding2010 5th International Conference on Embedded and Multimedia Computing10.1109/EMC.2010.5575615(1-6)Online publication date: Aug-2010
      • (2009)A 140-MHz 94 K gates HD1080p 30-frames/s intra-only profile H.264 encoderIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2009.201351119:3(432-436)Online publication date: 1-Mar-2009
      • (2009)HDTV1080p H.264/AVC Encoder Chip Design and Performance AnalysisIEEE Journal of Solid-State Circuits10.1109/JSSC.2008.201079744:2(594-608)Online publication date: Mar-2009
      • Show More Cited By

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