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Dummy fill aware buffer insertion during routing

Published: 11 March 2007 Publication History

Abstract

This paper studies the impacts of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion during routing. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during routing. Our contributions are threefold. First, we introduce a fast dummy fill estimation algorithm based on [4], which is better than traditional linear programming (LP) algorithm and suitable for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effects on the interconnect capacitance. Third, further analysis shows that the influences on the intermediate layer are more than that on the global layer, and as the required metal layer density increases the influences become more serious. Experiments gave the similar results and verified the necessity of early dummy fill estimation. Our dummy fill aware buffer insertion during early routing is promising and necessary.

References

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BPTM. http://www-device.eecs.berkeley.edu/ptm.
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Y. Chen, P. Gupta, and A. Kahng. Performance-impact limited area fill synthesis. Proc. DAC, pages 22--27, 2003.
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Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky. Monte-carlo algorithms for layout density control. Proc. ASP-DAC, pages 523--528, 2000.
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W. Elmore. The transient analysis of iterativeness damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics, 19(1), 1948.
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L. V. Ginneken. Buffer placement in distributed rc-tree networks for minimal elmore delay. Proc of Internationa Symposium on Circuits and Systems, page 865--868, December 1990.
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L. He, A. Kahng, K. Tam, and J. Xiong. Variability-driven considerations in the design of integrated-circuit global interconnects. Proc. 21th Intl. VLSI Multilevel Interconnection (VMIC) Conf, pages 214--221, September 2004.
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L. He, A. Kahng, K. Tam, and J. Xiong. Simultaneous buffer insertion and wire sizing considering systematic cmp variation and random leff variation. ISPD, pages 78--85, 2005.
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W. Shi and Z. Li. A fast algorithm for optimal buffer insertion. IEEE Trans. Computer-Aidede Design, 24(6):879--891, June 2005.
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R. Tian, D. F. Wong, and R. Boone. Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. TCAD, 20(7):902--910, July 2001.
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  • (2008)Full-chip routing system for reducing Cu CMP & ECP variationProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404386(10-15)Online publication date: 1-Sep-2008

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 March 2007

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Author Tags

  1. DFM
  2. VLSI
  3. buffer insertion
  4. dummy fill
  5. routing

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GLSVLSI07
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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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  • (2008)Full-chip routing system for reducing Cu CMP & ECP variationProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404386(10-15)Online publication date: 1-Sep-2008

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