skip to main content
10.1145/1228784.1228799acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Probabilistic gate-level power estimation using a novel waveform set method

Published: 11 March 2007 Publication History

Abstract

A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each circuit node is estimated. Existing methods have local glitch filtering approaches that fail to model this phenomenon correctly. Glitches originated from a node may be filtered in some, but not necessarily all, of its successor nodes. Our waveform set approach allows us to utilize a global glitch filtering technique that can model the removal ofglitches in more detail. It produces error free estimates for tree structured circuits. For other circuit, experimental results using the ISCAS'85 benchmarks show that the waveform set method generally provides significantly better estimates of the transition density compared to previous techniques.

References

[1]
M.A. Cirit. Estimating dynamic power consumption of CMOS circuits. In Proc. ICCAD, pages 534--537, November 1987.
[2]
F. Najm, R. Burch, P. Yang, and I. Hajj. Crest - a current estimator for cmos circuits. In Proc. IEEE Intl. Conf. Computer-Aided Design, pages 204--207, November 1988.
[3]
M.G. Xakellis and F.N. Najm. Statistical estimation of the switching activity in digital circuits. In Proc. of DAC, pages 728--733, 1994.
[4]
C.S. Ding, C.Y. Tsui, and M. Pedram. Gate-level power estimation using tagged probabilistic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 17:1099--1107, November 1998.
[5]
F. Hu and V.D. Agrawal. Dual-transition glitch filtering in probabilistic waveform power estimation. In Proc. 15th ACM Great Lakes symposium on VLSI, pages 357--360, April 2005.
[6]
F. Hu and V.D. Agrawal. Enhanced dual-transition probabilistic power estimation with selective supergate analysis. In Proc. Intl. Conference on Computer Design, pages 366--369, October 2005.
[7]
S. Bhanja and N. Ranganathan. Swtiching activity estimation of vlsi circuits using bayesian networks. IEEE Trans. Very Large Scale Integr. Syst., 11(4):558--567, 2003.
[8]
W.C. Tsai, C.B. Shung, and D.C. Wang. Accurate logic-level power simulation using glitch filtering and estimation. In Circuits and Systems, IEEE Asia Pacific Conf. on, pages 314--317, Nov 1996.
[9]
P. Israsena and S. Summerfield. Novel pattern-based power estimation tool with accurate glitch modeling. In Proc. ISCAS, pages 721--724, May 2000.
[10]
S. Theoharis, G. Theodoridis, D. Soudris, C. Goutis, and A. Thanailakis. A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of systems architecture, 48(4--5):113--124, 2002.
[11]
F.N. Najm. Power estimation techniques for integrated circuits. In Proc. Intl. Conf. on Computer-aided design, pages 492--499, 1995.
[12]
F. Najm. Transition density: A new measure of activity in digital circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12:310--323, February 1992.
[13]
F.N. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and allSystems, 10:1372--1381, November 1990.
[14]
S.C. Seth, L. Pan, and V.D. Agrawal. Predict - probabilistic estimation of digital circuit testability. In Proc. Fault Tolerant Computing Symposium, pages 220--225, June 1985.
[15]
T. Stornetta and F. Brewer. Implementation of an efficient parallel bdd package. In Proc. Design Automation Conference, pages 641--644, June 1996.
[16]
B. Kapoor. Improving the accuracy of circuit activity measurement. In Proc. Design Automation Conference, pages 734--739, June 1994.
[17]
R. Marculescu, D. Marculescu, and M. Pedram. Switching activity analysis considering spatiotemporal correlations. In Proc. IEEE/ACM Intl. Conference on Computer Aided Design, pages 294--299, November 1994.
[18]
S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Riccó. Estimate of signal probability in combinational logic networks. In Proc. 1st European Test Conf., pages 132--138, 1989.

Cited By

View all
  • (2011)Dynamic Power Estimation for Motion Estimation HardwareProceedings of the 2011 14th Euromicro Conference on Digital System Design10.1109/DSD.2011.40(279-282)Online publication date: 31-Aug-2011
  • (2009)Power Optimization of Parallel Multipliers in Systems with Variable Word-LengthIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-95948-9_11(103-115)Online publication date: 2009
  • (2008)Power optimization of weighted bit-product summation tree for elementary function generator2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541649(1240-1243)Online publication date: May-2008
  • Show More Cited By

Index Terms

  1. Probabilistic gate-level power estimation using a novel waveform set method

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. combinational logic
      2. gate-level
      3. probabilistic power estimation
      4. probability waveform
      5. transition density

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)3
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2011)Dynamic Power Estimation for Motion Estimation HardwareProceedings of the 2011 14th Euromicro Conference on Digital System Design10.1109/DSD.2011.40(279-282)Online publication date: 31-Aug-2011
      • (2009)Power Optimization of Parallel Multipliers in Systems with Variable Word-LengthIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-95948-9_11(103-115)Online publication date: 2009
      • (2008)Power optimization of weighted bit-product summation tree for elementary function generator2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541649(1240-1243)Online publication date: May-2008
      • (2007)Power optimized partial product reduction interconnect ordering in parallel multipliersNorchip 200710.1109/NORCHP.2007.4481034(1-6)Online publication date: Nov-2007

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media