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Robust wiring networks for DfY considering timing constraints

Published: 11 March 2007 Publication History

Abstract

In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

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Cited By

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  • (2020)Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield ImprovementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294198128:3(736-749)Online publication date: Mar-2020
  • (2012)Resource-constrained link insertion for delay reductionIntegration10.1016/j.vlsi.2012.02.00745:4(349-356)Online publication date: Sep-2012
  • (2010)Resource-constrained timing-driven link insertion for critical delay reductionProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785510(119-122)Online publication date: 16-May-2010
  • Show More Cited By

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 11 March 2007

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      Author Tags

      1. design for yield
      2. open defects
      3. redundant wiring
      4. timing constraint aware

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      View all
      • (2020)Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield ImprovementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294198128:3(736-749)Online publication date: Mar-2020
      • (2012)Resource-constrained link insertion for delay reductionIntegration10.1016/j.vlsi.2012.02.00745:4(349-356)Online publication date: Sep-2012
      • (2010)Resource-constrained timing-driven link insertion for critical delay reductionProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785510(119-122)Online publication date: 16-May-2010
      • (2009)How to consider shorts and guarantee yield rate improvement for redundant wire insertionProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687407(33-38)Online publication date: 2-Nov-2009
      • (2009)Redundant wire insertion for yield improvementProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531635(409-412)Online publication date: 10-May-2009
      • (2009)Optimal transformation of non-tree topologies for timing analysis2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)10.1109/PRIMEASIA.2009.5397446(69-72)Online publication date: Nov-2009
      • (2008)Considering possible opens in non-tree topology wire delay calculationProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366118(17-22)Online publication date: 4-May-2008
      • (2008)Design of robust signal and clock networksPAMM10.1002/pamm.2007004687:1(1070205-1070206)Online publication date: 7-Sep-2008
      • (2007)Concurrent wire spreading, widening, and fillingProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278569(350-353)Online publication date: 4-Jun-2007

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