skip to main content
10.1145/1228784.1228802acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Simultaneous reduction in test data volume and test time for TRC-reseeding

Published: 11 March 2007 Publication History

Abstract

A novel technique for reducing the test data volumes and the test application time of reseeding based on Twisted-ring counters is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes. The imposed hardware overhead is very small (only a small test control logic and three counters) since it is confined to just one extra bit per seed and a control word, named ORVECTOR, whose length is shorter than that of seed. The test-sequence-length-reduction technique requires 47% fewer test vectors for all ISCAS'89 benchmark circuits than of the original technique. Along with the test-sequence-length-reduction technique, a more efficient seed-selection algorithm targeting the minimization of the volumes of the selected seed for the test-per-clock, TRC-based, test set embedding case is presented. The seed-selection-algorithm requires 20% fewer seed for all ISCAS'89 benchmark circuits, because of the stored control word, requires 11% less the test-data storage that of the original technique. The proposed technique which combines the seed-selection-algorithm with the test-sequence-length-reduction scheme, delivers results with fewer seeds and much shorter test sequences than the already proposed approaches.

References

[1]
V. Agrawal, C. Kime, K. Saluja, "A tutorial on built-in self test," IEEE Design & Test of Computers, March 1993, pp. 73--80.
[2]
Andreas Steininger, "Testing and built-in self-test -A survey," Journal of Systems Architecture, vol. 46, 2000, pp. 721--747.
[3]
Huan-Chih Tsai, Kwang-Ting Cheng, and Sudipta Bhawmik, "On Improving Test Quality of Scan-Based BIST," IEEE Trans. Computer-Aided of Integrated Circuits and Systems, vol. 15, Aug. 2000, pp 928--938.
[4]
P. H. Bardell and W. H. McAnney, "Self-testing of multichip logic modules," Int. Test Conf., Nov. 1982, pp. 200--204.
[5]
B. Konemann, J. Mucha, and C. Zwiehoff, "Built-in logic block observation technique," Int. Test Conf., Oct. 1979, pp. 37--41.
[6]
A. Krasniewski and S. Pilarski, "Circular self-test path: A low-cost BIST technique for VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 8, Jan. 1989, pp. 46--55.
[7]
Nur A. Touba, "Circular BIST With State Skipping," IEEE Trans. VLSI, vol. 10, Oct. 2002, pp. 668--672.
[8]
Krishnendu Chakrbarty, Brian T. Murray, and Vikram Iyengar, " Deterministic Built-in Test pattern Generation for High-Performance Circuits Using Twisted-Ring Counters," IEEE Trans. VLSI, vol. 8, Oct. 2000, pp. 633--636.
[9]
Krishnendu Chakrbarty, and Shivakumar S. waminathan, "Built-in Self Testing of High-Performance Circuits Using Twisted-Ring Counters," IEEE International Symposium on Circuits and Systems, May, 2000, pp.72--75.
[10]
E.J. McCluskey et al., "Test data compression," IEEE design Test Comp., vol.20, Mar/Apr. 2003, pp.76--87.
[11]
H.-S. Kim, and S. Kang, "Increasing encoding efficiency of LFSR reseeding-based test compression," IEEE Trans. CAD, vol. 25, May. 2006, pp. 913--917.
[12]
E. Kalligeros, D. Kaseridis, X. Kavousianos and D. Nikolos, "Reseeding-based Test Set Embedding with Reduced Test Sequences," IEEE International Symposium on Quality Electronic Design, March, 2005, pp.226--231.

Cited By

View all
  • (2019)An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring CountersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225315532:8(1254-1264)Online publication date: 4-Jan-2019
  • (2016)Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241341635:2(274-284)Online publication date: Mar-2016
  • (2015)Ring Counter Based ATPG for Low Transition Test Pattern GenerationThe Scientific World Journal10.1155/2015/7291652015:1Online publication date: 14-May-2015
  • Show More Cited By

Index Terms

  1. Simultaneous reduction in test data volume and test time for TRC-reseeding

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. built-in self test
      2. encoded vector
      3. twisted-ring counter

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2019)An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring CountersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225315532:8(1254-1264)Online publication date: 4-Jan-2019
      • (2016)Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241341635:2(274-284)Online publication date: Mar-2016
      • (2015)Ring Counter Based ATPG for Low Transition Test Pattern GenerationThe Scientific World Journal10.1155/2015/7291652015:1Online publication date: 14-May-2015
      • (2015)Design and Implementation of an On-Chip Test Generation Scheme Based on Reconfigurable Run-Time Programmable and Multiple Twisted-Ring CountersProcedia Computer Science10.1016/j.procs.2015.02.05946(1409-1416)Online publication date: 2015
      • (2012)A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data VolumeProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.11(278-283)Online publication date: 19-Nov-2012
      • (2010)An ATPG for low power VLSI design using variable length ringcounter & LFSR2010 International Conference on Signal and Image Processing10.1109/ICSIP.2010.5697517(457-461)Online publication date: Dec-2010
      • (2010)A test set embedding approach based on twisted-ring counter with few seedsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00143:1(81-100)Online publication date: 1-Jan-2010
      • (2009)A new low power test pattern generator using a variable-length ring counterProceedings of the 2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810302(248-252)Online publication date: 16-Mar-2009

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media