skip to main content
10.1145/1228784.1228803acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

SEU mitigation for sram-based fpgas through dynamic partial reconfiguration

Published: 11 March 2007 Publication History

Abstract

This paper presents a methodology for designing reliable systems implemented on Field Programmable Gate Arrays (FPGAs), able to cope with the effects of Single Event Upset (SEU) faults, causing bit-flips in SRAM memory. The approach exploits FPGAs' partial dynamic re-configuration capability to mitigate the effects of SEUs, affecting either the user SRAM memory or the configuration memory itself. The goal is to detect the occurrence of faults and either to restart computation or to trigger a reconfiguration of part of the device in order to recover from them. The proposal allows the exploration of different solutions, characterized byvarying costs and benefits, allowing the designer to select the most convenient trade-off. Results of the application of the methodology to a case study are reported to evaluate the proposed approach.

References

[1]
F. Ziegler et al. Terrestrial cosmic rays and soft errors. IBM Journal of Research and Develop., 40(1), 1996.
[2]
H. T. Nguyen and Y. Yagil. A systematic approach to SER estimation and solutions. In Proc. IEEE Int. Reliability Physics Symp., pages 60--70, 2003.
[3]
J. Barth, C. Dyer, and E. Stassinopoulos. Space, atmospheric, and terrestrial radiation environments. IEEE Trans. Nuclear Science, 50(3):466--482, June 2003.
[4]
C. Stroud, S. Konala, Ping Chen, and M. Abramovici. Built-in self-test of logic blocks in FPGAs. In Proc. 14th IEEE VLSI Test Symp., pages 387--392, 1996.
[5]
M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya, and V. Verma. Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications. In Proc. IEEE Int. Test Conference, page 973, 1999.
[6]
C. Carmichael, E. Fuller, P. Blain, and M. Caffrey. SEU mitigation techniques for Virtex FPGAs in space application. In MAPLD'99 Poster, page 24, 1999.
[7]
E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula. Radiation Testing Update, SEU Mitigation, and Availability Analysis of the Virtex FPGA for Space Reconfigurable Computing. In IEEE Nuclear and Space Radiation Effects Conference, 2000.
[8]
M. Abramovici, C. Stroud, B. Skaggs, and J. Emmert. Improving On-Line BIST-Based Diagnosis for Roving STARs. In Proc. 6th IEEE Int. On-Line Testing Workshop, page 31, 2000.
[9]
C. Carmichael, M. Caffrey, and A. Salazar. Correcting Single-Event Upsets Through Virtex Partial Configuration. Xilinx Application Notes 216, 2000.
[10]
F. Lima, C. Carmichael, J. Fabula, R. Padovani, R. Reis. A fault injection analysis of virtex fpga tmr design methodology. In Proc. European Radiation and Its Effects on Components and Systems Conference, pages 275--282, 2001.
[11]
C. Carmichael. Triple Module Redundancy Design Techniques for Virtex FPGAs. Xilinx Application Notes 197, 2006.
[12]
F. Lima, L. Carro, and R. Reis. Designing fault tolerant systems into SRAM-based FPGAs. In Proc. of the 40th Conf. on Design Automation, pages 650--655, 2003.
[13]
L. Sterpone and M. Violante. A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. on Computers, 55(6):732--744, 2006.
[14]
R. Velazco T. Calin, M. Nicolaidis. Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nuclear Science, 43(6):2874--2878, 1996.
[15]
D. Lim and M. Peattie. Two Flows for Partial Reconfiguration: Module Based or Difference Based. Xilinx Application Notes 290 (v.1.2), May 2004.
[16]
F. Lima Kastensmidt, L. Sterpone, M. Sonza Reorda, and L. Carro. On the optimal design of triple modular redundancy logic for sram-based. In IEEE Proc. Design, Automation and Test in Europe Conference, pages 1290--1295, 2005.
[17]
D. P. Sieworek and R. S. Swarz. The Theory and Practice of Reliable System Design. Digital Press, 1982.
[18]
S. Kelem. Virtex Series Configuration Architecture User Guide. Xilinx Application Notes 151, 2003.
[19]
J. Daemen, M. Peeters, G. Van Asshe, and V. Rijmen. Nessie proposal: Noekeon.
[20]
http://www.xilinx.com/products/design_tools/logic_design/design_entry/floorplanner.htm

Cited By

View all
  • (2021)Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication2021 IEEE Microelectronics Design & Test Symposium (MDTS)10.1109/MDTS52103.2021.9476122(1-6)Online publication date: 18-May-2021
  • (2020)A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301064728:10(2134-2145)Online publication date: Oct-2020
  • (2019)Field Programmable Gate Array Applications—A Scientometric ReviewComputation10.3390/computation70400637:4(63)Online publication date: 11-Nov-2019
  • Show More Cited By

Index Terms

  1. SEU mitigation for sram-based fpgas through dynamic partial reconfiguration

        Recommendations

        Comments

        Information & Contributors

        Information

        Published In

        cover image ACM Conferences
        GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
        March 2007
        626 pages
        ISBN:9781595936059
        DOI:10.1145/1228784
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Sponsors

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 11 March 2007

        Permissions

        Request permissions for this article.

        Check for updates

        Author Tags

        1. SEU
        2. fault detection
        3. partial dynamic reconfiguration

        Qualifiers

        • Article

        Conference

        GLSVLSI07
        Sponsor:
        GLSVLSI07: Great Lakes Symposium on VLSI 2007
        March 11 - 13, 2007
        Stresa-Lago Maggiore, Italy

        Acceptance Rates

        Overall Acceptance Rate 312 of 1,156 submissions, 27%

        Upcoming Conference

        GLSVLSI '25
        Great Lakes Symposium on VLSI 2025
        June 30 - July 2, 2025
        New Orleans , LA , USA

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)1
        • Downloads (Last 6 weeks)0
        Reflects downloads up to 27 Jan 2025

        Other Metrics

        Citations

        Cited By

        View all
        • (2021)Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication2021 IEEE Microelectronics Design & Test Symposium (MDTS)10.1109/MDTS52103.2021.9476122(1-6)Online publication date: 18-May-2021
        • (2020)A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301064728:10(2134-2145)Online publication date: Oct-2020
        • (2019)Field Programmable Gate Array Applications—A Scientometric ReviewComputation10.3390/computation70400637:4(63)Online publication date: 11-Nov-2019
        • (2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
        • (2017)Soft error high speed correction by interruption scrubbing method in FPGA for embedded control system2017 IEEE 2nd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)10.1109/ITNEC.2017.8284809(634-641)Online publication date: Dec-2017
        • (2017)A Review on SEU Mitigation Techniques for FPGA Configuration MemoryIETE Technical Review10.1080/02564602.2016.126590535:2(157-168)Online publication date: 23-Jan-2017
        • (2015)A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2015.7238095(1-7)Online publication date: Jun-2015
        • (2015)Generic scrubbing-based architecture for custom error correction algorithms2015 International Symposium on Rapid System Prototyping (RSP)10.1109/RSP.2015.7416555(112-118)Online publication date: Oct-2015
        • (2015)A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2015.7245735(202-209)Online publication date: Jul-2015
        • (2014)A novel methodology to increase fault tolerance in autonomous FPGA-based systems2014 IEEE 20th International On-Line Testing Symposium (IOLTS)10.1109/IOLTS.2014.6873677(87-92)Online publication date: Jul-2014
        • Show More Cited By

        View Options

        Login options

        View options

        PDF

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader

        Figures

        Tables

        Media

        Share

        Share

        Share this Publication link

        Share on social media