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Co-evolutionary high-level test synthesis

Published: 11 March 2007 Publication History

Abstract

The main approach of this paper is utilizing bio-inspired evolutionary strategies for high level test synthesis. In this paper a genetic algorithm (GA) is implemented to schedule a data-flow graph considering latency. Also, module binding is performed with another GA concurrently, considering resource constraints. The register allocation is performed using another GA which minimizes the number of registers. Then a co-evolutionary strategy merges the results of these three solutions, targeting testability improvement. Experimental results show using the proposed approach results in improvement in fault coverage with no or negligible overhead in area and delay.

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HOPE (version 2.0), Dong S. Ha ([email protected]), Web: http://www.ee.vt.edu/ha, Virginia Polytechnic Institute & State University.

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  • (2008)Co-evolutionary reliability-oriented high-level synthesis2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541845(2026-2029)Online publication date: May-2008

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        cover image ACM Conferences
        GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
        March 2007
        626 pages
        ISBN:9781595936059
        DOI:10.1145/1228784
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        Published: 11 March 2007

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        Author Tags

        1. co-evolutionary algorithm
        2. genetic algorithm
        3. high-level test synthesis
        4. module binding
        5. register allocation
        6. scheduling

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        March 11 - 13, 2007
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        • (2008)Co-evolutionary reliability-oriented high-level synthesis2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541845(2026-2029)Online publication date: May-2008

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