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Analysis of data dependence of leakage current in CMOS cryptographic hardware

Published: 11 March 2007 Publication History

Abstract

A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.

References

[1]
P. Kocher, J. Jaffe and B. Jun, "Differential Power Analysis," Advances in Cryptology, Santa Barbara, Aug. 1999, Lecture Notes in Computer Science, vol. 1666, 1999, pp. 388--397.]]
[2]
M. Bucci, M. Guglielmo, R. Luzzi, and A. Trifiletti, "A power consumption randomization countermeasure for DPA resistant cryptographic processors. in PATMOS, 2004, pp. 481--490.]]
[3]
A. Shamir, "Protecting smart cards from passive power analysis with detached power supplies," in CHES '00: Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems. London, UK: Springer-Verlag, 2000, pp. 71--77.]]
[4]
S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction" International Symposium on Low Power Electronics and Design 2001, pp. 195--200.]]
[5]
S. Bobba, and I. N. Hajj "Maximum leakage power estimation for CMOS circuits" IEEE Proc. on Low Power Design, March 1999 pp. 116--124.]]
[6]
Antoni Ferrè, and Joan Figueras "On estimating leakage power consumption for submicron CMOS digital circuits" IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation, Louvain La Neuve, Belgium, September 1997.]]
[7]
Afshin Abdollahi, Farzan Fallah, and Massoud Pedram "Leakage current reduction in CMOS VLSI circuits by input vector controll," IEEE Trans. on VLSI Systems, vol. 12, no. 2, 2004, pp. 140--154.]]
[8]
Zhanping Chen, Liqiong Wei, Mark Johnson, and Kaushik Roy "Estimation of standby leakage power in CMOS circuits considering accurate modelling of transistor stacks" International Symposium on Low Power Electronics and Design, Aug 1998 pp. 239--24.]]
[9]
Yannis Tsividis "Operation and Modeling of the Transistor MOS" second edition, Oxford University Press, 2003.]]
[10]
Geoff Merrett and Bashir M. Al-Hashimi "Leakage power analysis and comparison of deep submicron logic gates" IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation, pp. 198--207, Santorini, Greece, 2004.]]
[11]
R. Anderson, E. Biham, and L. Kundsen, A proposal for the Advanced Encryption Standard, AES proposal, 1998, available at http://www.cl.cam.ac.uk/ftp/users/rja14/serpent.pdf.]]
[12]
M. Aigner, S. Mangard, F. Menichelli, R. Menicocci, M. Olivieri, T. Popp, G. Scotti, A. Trifiletti, "A. Side channel analysis resistant design flow"; IEEE International Symposium on Circuits and Systems, 21-24 May 2006.]]

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  • (2022)A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842186(504-508)Online publication date: 19-Jun-2022
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  1. Analysis of data dependence of leakage current in CMOS cryptographic hardware

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. cryptographic hardware
      2. leakage power consumption
      3. side channel analysis

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      March 11 - 13, 2007
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      View all
      • (2024)Beware Your Standard Cells! On Their Role in Static Power Side-Channel AttacksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339473643:12(4439-4452)Online publication date: Dec-2024
      • (2022)A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842186(504-508)Online publication date: 19-Jun-2022
      • (2021)Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging GoalApplied Sciences10.3390/app1115714311:15(7143)Online publication date: 2-Aug-2021
      • (2021)Masked SABL: A Long Lasting Side-Channel Protection Design MethodologyIEEE Access10.1109/ACCESS.2021.30907529(90455-90464)Online publication date: 2021
      • (2020)Static Power Side-Channel Analysis—An Investigation of Measurement FactorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294814128:2(376-389)Online publication date: Mar-2020
      • (2020)Standard Cell Tuning Enables Data-Independent Static Power Consumption2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS50862.2020.9095656(1-6)Online publication date: Apr-2020
      • (2019)CMOS Illumination Discloses Processed Data2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00062(381-388)Online publication date: Aug-2019
      • (2018)Leakage power analysis attacksIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.201941157:2(355-367)Online publication date: 13-Dec-2018
      • (2018)Survey on power analysis attacks and its impact on intelligent sensor networksIET Wireless Sensor Systems10.1049/iet-wss.2018.51578:6(295-304)Online publication date: 1-Dec-2018
      • (2017)Static power side-channel analysis of a threshold implementation prototype chipProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130692(1324-1329)Online publication date: 27-Mar-2017
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