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View all- Lee NJiang J(2021)Constraint Solving for Synthesis and Verification of Threshold Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301544140:5(904-917)Online publication date: May-2021
- Chen YZheng LWong F(2019)Optimization of Threshold Logic Networks with Node Merging and Wire ReplacementACM Transactions on Design Automation of Electronic Systems10.1145/335874824:6(1-18)Online publication date: 14-Oct-2019
- Devadoss RPaul KBalakrishnan M(2019)Majority Logic: Prime Implicants and n-Input Majority Term Equivalence2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2019.00098(464-469)Online publication date: Jan-2019
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