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Transition-activity aware design of reduction-stages for parallel multipliers

Published: 11 March 2007 Publication History

Abstract

We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least significant bits. The same is the case for individual signals within the multiplier. Our interconnect reorganization exploits this to reduce the overall switching activity, thus reducing the multiplier's power consumption. We have developed a CAD tool that reorganizes the connections within the multiplier architecture in an optimized way. Since the applied heuristic requires power estimation, we have also developed a very fast estimator fine tuned for parallel multipliers. The CAD tool automatically generates gate-level VHDL code for the optimizedmultipliers. This code and code for unoptimized multipliers have been compared using state of the art power estimation tools. The reduction in power consumption ranges from 7% up to 23% and can be achieved without any noticeable overhead in performance and area.

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Cited By

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  • (2024)Optimizing Multiplier Performance with Advanced PTL-Based AND Gate and Efficient Full Adder Design2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC)10.1109/ICSSEECC61126.2024.10649451(295-300)Online publication date: 28-Jun-2024
  • (2021)An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applicationsMicroelectronics Journal10.1016/j.mejo.2021.105287118:COnline publication date: 1-Dec-2021
  • (2015)Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication2015 49th Asilomar Conference on Signals, Systems and Computers10.1109/ACSSC.2015.7421228(722-726)Online publication date: Nov-2015
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  1. Transition-activity aware design of reduction-stages for parallel multipliers

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      Published: 11 March 2007

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      Author Tags

      1. parallel multiplier
      2. partial product reduction
      3. power consumption
      4. transition activity

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      March 11 - 13, 2007
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      Cited By

      View all
      • (2024)Optimizing Multiplier Performance with Advanced PTL-Based AND Gate and Efficient Full Adder Design2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC)10.1109/ICSSEECC61126.2024.10649451(295-300)Online publication date: 28-Jun-2024
      • (2021)An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applicationsMicroelectronics Journal10.1016/j.mejo.2021.105287118:COnline publication date: 1-Dec-2021
      • (2015)Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication2015 49th Asilomar Conference on Signals, Systems and Computers10.1109/ACSSC.2015.7421228(722-726)Online publication date: Nov-2015
      • (2008)Power optimization of weighted bit-product summation tree for elementary function generator2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541649(1240-1243)Online publication date: May-2008
      • (2007)Switching activity reduction of MAC-based FIR filters with correlated input dataProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391858(526-535)Online publication date: 3-Sep-2007
      • (2007)Power optimized partial product reduction interconnect ordering in parallel multipliersNorchip 200710.1109/NORCHP.2007.4481034(1-6)Online publication date: Nov-2007
      • (2007)Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input DataIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-74442-9_51(526-535)Online publication date: 2007

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