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GALS SoC interconnect bus for wireless sensor network processor platforms

Published: 11 March 2007 Publication History

Abstract

The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.

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  • (2022)Design and Implementation of AXI4-lite Interface in Zynq SoC2022 IEEE Delhi Section Conference (DELCON)10.1109/DELCON54057.2022.9753421(1-4)Online publication date: 11-Feb-2022
  • (2017)Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks2017 IEEE/ACS 14th International Conference on Computer Systems and Applications (AICCSA)10.1109/AICCSA.2017.26(1163-1169)Online publication date: Oct-2017
  • (2012)Low Energy Online Self-Test of Embedded Processors in Dependable WSN NodesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2011.179:1(86-100)Online publication date: 1-Jan-2012
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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. GALS
      2. SoC bus
      3. WSN
      4. application specific bus
      5. low power
      6. system on chip bus
      7. wireless sensor network

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      March 11 - 13, 2007
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      View all
      • (2022)Design and Implementation of AXI4-lite Interface in Zynq SoC2022 IEEE Delhi Section Conference (DELCON)10.1109/DELCON54057.2022.9753421(1-4)Online publication date: 11-Feb-2022
      • (2017)Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks2017 IEEE/ACS 14th International Conference on Computer Systems and Applications (AICCSA)10.1109/AICCSA.2017.26(1163-1169)Online publication date: Oct-2017
      • (2012)Low Energy Online Self-Test of Embedded Processors in Dependable WSN NodesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2011.179:1(86-100)Online publication date: 1-Jan-2012
      • (2010)Low-power TinyOS tuned processor platform for wireless sensor network motesACM Transactions on Design Automation of Electronic Systems10.1145/1754405.175440815:3(1-17)Online publication date: 10-Jun-2010
      • (2010)Energy optimal on-line Self-Test of microprocessors in WSN nodes2010 IEEE International Conference on Computer Design10.1109/ICCD.2010.5647693(376-383)Online publication date: Oct-2010
      • (2009)Energy efficient architecture of sensor network node based on compression acceleratorProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531572(117-120)Online publication date: 10-May-2009

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