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A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS

Published: 11 March 2007 Publication History

Abstract

A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CPLDs. The presented approach is an alternative to the classical method based on two-level minimization of separate single-output functions. The essence of the presented method is to search for multi-output implicants that can be shared by several functions. This approach presents a original form for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with the common output part. The graph analyses allow to effective implementation of multi-output function in PAL-based devices. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing low number of product terms.

References

[1]
Anderson J. H., Brown S. D., Technology mapping for large complex PLDs, Proceedings of Design Automation Conference, DAC'98, 15--19 January, 1998, 698--703.
[2]
Chen S., Hwang T., Liu C., A technology mapping algorithm for CPLD architectures, IEEE International. Conference on Field - Programmable Technology, Hong Kong, 2002, 204--210.
[3]
Kania D., Two-level logic synthesis on PALs, Electronics Letters, Vol.35, No. 11, 1999, 879--880.
[4]
Kania D., The Logic Synthesis for the PAL-based CPLDs, Wydawnictwo Politechniki Slaskiej, nr 14, Gliwice 2004 (in polish).
[5]
Micheli G, Synthesis and optimization of digital circuits, McGraw-Hill International Ed.

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  1. A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. CPLDs
    2. logic synthesis
    3. technology mapping

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    GLSVLSI07
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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    • (2020)IntroductionTechnology Mapping for LUT-Based FPGA10.1007/978-3-030-60488-2_1(1-14)Online publication date: 8-Nov-2020
    • (2019)Graph of Outputs in the Process of Synthesis Directed at CPLDsMathematics10.3390/math71211717:12(1171)Online publication date: 3-Dec-2019
    • (2019)A Technology Mapping of FSMs Based on a Graph of Excitations and OutputsIEEE Access10.1109/ACCESS.2019.28952067(16123-16131)Online publication date: 2019
    • (2018)Area and speed oriented synthesis of FSMs for PAL-based CPLDsMicroprocessors & Microsystems10.1016/j.micpro.2011.06.00436:1(45-61)Online publication date: 28-Dec-2018
    • (2017)A technology mapping based on graph of excitations and outputs for finite state machines10.1063/1.5012398(120006)Online publication date: 2017
    • (2015)Technology mapping based on modified graph of outputs10.1063/1.4938790(060003)Online publication date: 2015
    • (2014)Analysis of implementation opportunities for selected conventional counter-based circuits in selected FPGA structures in terms of time performance2014 International Conference on Applied and Theoretical Electricity (ICATE)10.1109/ICATE.2014.6972604(1-7)Online publication date: Oct-2014
    • (2013)ExperimentsFinite State Machine Logic Synthesis for Complex Programmable Logic Devices10.1007/978-3-642-36166-1_8(123-159)Online publication date: 2013
    • (2009)CPLD-oriented Synthesis of Finite State MachinesProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.173(521-528)Online publication date: 27-Aug-2009

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