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Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Published: 11 March 2007 Publication History

Abstract

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18μm CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

References

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J. Ostermann, etal. Video coding with h.264/avc: Tools, performance, and complexity. IEEE Circuits and Systems Magazine, 4(1):7--28, First Quarter 2004.
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Y. W. Huang, T. C. Wang, B. Y. Hsieh, and L. G. Chen. Hardware architecture design for variable block size motion estimation in mpeg-4 avc/jvt/itu-t h.264. In Proceedings of ISCAS 2003, volume 2, pages 796--799, May 2003.
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C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen. Analysis and architecture design of variable block-size motion estimation for h.264/avc. IEEE Circuits and Systems I, 53(3):578--593, March 2006.
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Z. Y. Liu, Y. Song, T. Ikenaga, and S. Goto. A fine-grain scalable and low memory cost variable block size motion estimation architecture for h.264/avc. IEICE Transactions on Electronics, E89-C(12):1928--1936, December 2006.
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M. Kim, I. Hwang, and S. I. Chae. A fast vlsi architecture for full-search variable block size motion estimation in mpeg-4 avc/h.264. In Proceedings of ASP-DAC 2005, volume 1, pages 631--634, January 2005.
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S. Y. Yap and J. V. McCanny. A vlsi architecture for variable block size video motion estimation. IEEE Transactions on Circuits and Systems II: Express Briefs, 51(7):384--389, October 2004.
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J. Vanne, E. Aho, T. D. Hamalainen, and K. Kuusilinna. A high-performance sum of absolute difference implementation for motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 16(7):876--883, July 2006.
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Cited By

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  • (2019)Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVCJournal of Signal Processing Systems10.5555/2444517.244453771:2(111-121)Online publication date: 17-Jan-2019
  • (2019)UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise addersJournal of Real-Time Image Processing10.1007/s11554-019-00934-2Online publication date: 11-Dec-2019
  • (2018)Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVCIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e91-a.4.987E91-A:4(987-997)Online publication date: 21-Dec-2018
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  1. Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. H.264
      2. VLSI
      3. variable block size motion estimation

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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      Cited By

      View all
      • (2019)Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVCJournal of Signal Processing Systems10.5555/2444517.244453771:2(111-121)Online publication date: 17-Jan-2019
      • (2019)UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise addersJournal of Real-Time Image Processing10.1007/s11554-019-00934-2Online publication date: 11-Dec-2019
      • (2018)Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVCIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e91-a.4.987E91-A:4(987-997)Online publication date: 21-Dec-2018
      • (2018)A Low Cost Architecture for Variable Block Size Motion EstimationJournal of Signal Processing Systems10.1007/s11265-011-0589-768:1(127-138)Online publication date: 27-Dec-2018
      • (2017)IO and data management for infrastructure as a service FPGA acceleratorsJournal of Cloud Computing: Advances, Systems and Applications10.1186/s13677-017-0089-96:1(1-23)Online publication date: 1-Dec-2017
      • (2017)An efficient hardware realization of diamond search algorithm for motion estimation task in video compression applications2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)10.1109/ICMDCS.2017.8211693(1-6)Online publication date: Aug-2017
      • (2014)A high-performance VLSI architecture for variable block size motion estimation2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE)10.1109/GCCE.2014.7031303(123-124)Online publication date: Oct-2014
      • (2013)Gigabyte-scale alignment of biological sequences: A case study of IO bandwidth reconfiguration for FPGA acceleration2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2013.6567789(1-4)Online publication date: May-2013
      • (2012)Reconfigurable architecture for VBSME with variable pixel precisionACM Transactions on Reconfigurable Technology and Systems10.1145/2133352.21333555:1(1-11)Online publication date: 23-Mar-2012
      • (2012)A VLSI architecture for three-step search with variable block size motion vectorThe 1st IEEE Global Conference on Consumer Electronics 201210.1109/GCCE.2012.6379545(628-631)Online publication date: Oct-2012
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