skip to main content
10.1145/1228784.1228827acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Compiler assisted architectural exploration for coarse grained reconfigurable arrays

Published: 11 March 2007 Publication History

Abstract

A large number of factors influence the hardware cost and the mapping efficiency of applications on coarse grain reconfigurable architectures. This paper investigates for the first time in a unified way the four factors that are directly related with the efficiency of a coarse grain reconfigurable array architecture namely; the area the clock frequency, the scheduling efficiency and performance. An exploration framework has been build for estimating the values of the 4 a forementioned factors for different architecture alternatives. The exploration framework is composed of an existing retargetable compiler framework from which we estimate the mapping efficiency and the parametric realization of the coarse grained reconfigurable array architecture in hardware description language from which we estimate the clock frequency and the area of each architecture instance. The experiments refer to different architecture alternatives in terms of the processing elements' interconnection network, the register files' size, their number of input/output ports, and finally the available bandwidth. Totally 72 architecture scenarios have been studied revealing how each characteristic influences performance and area for efficiently make design decisions.

References

[1]
R. Hartenstein, "A decade of reconfigurable computing: A visionary retrospective, Proc. of ACM/IEEE DATE '01, pp. 642--649.]]
[2]
Pact Corporation, "The XPP white Paper," Technical report, www.pactcorp.com, 2005.]]
[3]
B. Mei, S. Vernalde, D. Verkest, R. Lauwereins, "Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study," in Proc. Of DATE '04, vol 2, pp. 1224--1229.]]
[4]
H. Singh, L. Ming-Hau, L. Guangming, et.al., "MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Communication-Intensive Applications," in IEEE Trans. on Computers, vol. 49, no. 5, pp. 465--481, May 2000.]]
[5]
Zion Kwok, S.J.E. Wilton, "Register File Architecture Optimization in coarse grained reconfigurable architecture," In Proc. 13th Annual IEEE Symp. on Field Programmable Custom Computing Machines 2005, pp 1--10.]]
[6]
Reiner W. Hartenstein, Th. Hoffman, and U. Nageldinger, "Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures," in Proc. PATMOS 2000 LNCS 1918, pp 118--128.]]
[7]
Leipo Yan, Thabipillai Srikanthan, Niu Gang, "Area and Delay Estimation for FPGA Implementation of Coarse Grained Reconfigurable Architectures," In Proc. of ACM LCTES June 2006, pp 182--188.]]
[8]
B. Mei, A. Lambechts, D. Verkest, J.Y. Mignolet and R. Lauwereins, "Architecture Exploration for a Reconfigurble Architecture Template," in IEEE Design & Test of Computers, vol.22 no.2 pp. 90--101, March-April 2005.]]
[9]
Seth Copen Goldstein, et.al., "PiperRench: A Coprocessor for Streaming Multimedia Acceleration," in Proc. IEEE Inter. Symp. Of Computer Architecture (ISCA 99), pp 28--40.]]
[10]
G. Dimitroulakos, M.D. Galanis, C.E Goutis, "Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures," in Proc. IEEE Int. Symp. Par. And Distr. Systems (IPDPS'06), pp 10, April 25--29,2006.]]
[11]
Texas Instruments Inc., www.ti.com, 2005.]]

Cited By

View all
  • (2011)BibliographyDesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(189-196)Online publication date: 14-Apr-2011

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 March 2007

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. architectural exploration
  2. coarse-grained reconfigurable arrays
  3. modulo scheduling
  4. reconfigurable computing

Qualifiers

  • Article

Conference

GLSVLSI07
Sponsor:
GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25
Great Lakes Symposium on VLSI 2025
June 30 - July 2, 2025
New Orleans , LA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 27 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2011)BibliographyDesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(189-196)Online publication date: 14-Apr-2011

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media