skip to main content
10.1145/1228784.1228829acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

RT level reliability enhancement by constructing dynamic TMRS

Published: 11 March 2007 Publication History

Abstract

This paper presents a novel and efficient approach for reliability enhancement at the RT level. The reliability enhancement is performed by utilizing the available resources of a design in their dead intervals. Such resources are used for constructing dynamic TMR structures that can change per clock cycle. In this method all resources participate in constructing TMR structures at least once per a system input to output flow.To evaluate the proposed fault tolerance technique we consider dependability, and area/latency overhead imposed on a circuit by applying our method. In order to evaluate dependability, faults are injected into our test circuits before and after applying our algorithm and fault coverage is measured. Experimental results show that after applying our method, fault coverage is significantly reduced indicating that the reliability of designs is improved.

References

[1]
Bayraktaroglu. I, and Orailoglu. A. Concurrent test for digital linear systems. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, 2001, 1775--791.
[2]
Bolchini, C. et al. Concurrent error detection at architectural level. In Proceedings of the 11th international symposium on System synthesis, 1998, 72--75.
[3]
Bushnell, M. L., and Agrawal, V. D. Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits. Kluwer Academic Publishers, 2000.
[4]
Hamilton, S. N., and Orailoglu, A. On-Line test for fault-secure fault identification. IEEE Trans. VLSI Systems, Vol. 8, No. 4, August 2000.
[5]
Johnson, B. W. Design and Analysis of Fault-Tolerant Digital Systems. Addison-Wesley, 1989.
[6]
Karri, R., and Iyer, B. Introspection: A register transfer level technique for concurrent error detection and diagnosis in data dominated designs. ACM Trans. Design Automation of Electronic Systems, Vol. 6, No. 4, 2001, 501--515.
[7]
Lee, M. T. High-Level Test Synthesis of Digital VLSI Circuits. Artech House, 1997.
[8]
Makris, Y., Bayraktaroglu, I., and Orailoglu, A. Enhancing reliability of RTL controller-datapath circuits via invariant-based concurrent test. IEEE Trans. Reliability, Vol. 53, No. 2, 2004.
[9]
Mitra, S. "Diversity Techniques for Concurrent Error Detection. Ph.D. Thesis, Stanford University, 2000.
[10]
Navabi, Z., Mirkhani, S., Lavasani, M., and Lombardi, F. Using RT level component descriptions for single stuck-at hierarchical fault simulation. Journal of electronic testing-Theory and Applications, Vol. 20, December 2004, 575--589.
[11]
Nicolaidis, M., and Zorian, Y. On-line testing for VLSI- A compendium of approaches. Journal of electronic testing-Theory and Applications, Vol. 12, No. 1-2, 1988, 7--20.
[12]
Oikonomakos, P., and Zwolinski, M. Using high-level synthesis to implement on-line testability. IEEE Real-Time Embedded System Workshop, Dec. 2001.
[13]
Oikonomakos, P., Zwolinski, M., and Al-hashimi, B. M. Versatile high-level synthesis of self-checking datapaths using an on-line testability metric. In Proceedings of. Design Automation and Test in Europe, March 2003.
[14]
Orailoglu, A., and Karri, R. Automatic synthesis of self-recovering VLSI systems. IEEE Trans. Computers, Vol. 45, No. 2, Feb. 1996.
[15]
Rao, W., Orailoglu, A., and Karri, R. Fault tolerant arithmetic with applications in nanotechnology based systems. In Proceedings of International Test Conference, 2004, 472--47.
[16]
Voyiatzis, I.and Paschalis, A. R-CBIST: An effective RAM-based input vector monitoring concurrent BIST technique. In Proceedings of International Test Conference, 1998.
[17]
Voyiatzis, I., et al. An efficient comparative concurrent built-in self test technique. In Proceedings of Asian Test Symposium, 1995.
[18]
Voyiatzis, I., et al. A concurrent built-in self test architecture based on a self-testing RAM. IEEE Trans. Reliability, Vol. 54, No. 1, March 2005.

Index Terms

  1. RT level reliability enhancement by constructing dynamic TMRS

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. RTL design
      2. TMR
      3. fault tolerant
      4. reliability

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 165
        Total Downloads
      • Downloads (Last 12 months)1
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media