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An asynchronous fpga logic cell implementation

Published: 11 March 2007 Publication History

Abstract

We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limitations on the size of the logic cell due to the stacking problem. To overcome this limitation we propose a novel method for implementing these templates. Our method uses standard single-rail computational circuits. It does not have any stacking problem and is not limited in size. The results show that a 4-input logic cell implemented by this method outperforms a previous 3-input logic cell by 16% in speed and 29% in power with a negligible area overhead.

References

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Lines, A. Pipelined Asynchronous Circuits. master's thesis, California Inst. of Technology, 1995.
[2]
Teifel, J. and Manohar, R. An Asynchronous Dataflow FPGA Architecture. IEEE Transactions on Computers, VOL. 53, NO. 11, Nobember 2004.
[3]
Ahmed, E. and Rose, J. The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 12, NO. 3, MARCH 2004.
[4]
Teifel, J. and Manohar, R. Programmable Asynchronous Pipeline Arrays. Proc. Int'l Conf. Field Programmable Logic and Applications, Sept. 2003.
[5]
Wong, C. G., Martin, A. and Thomas, P. An Architecture for Asynchronous FPGAs Proc. Int'l Conf. Field-Programmable Technology (FPT), Dec. 2003.
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Manohar R. and Martin, A.J. Slack Elasticity in Concurrent Computing. Proc. Int'l Conf. Math. of Program Construction, 1998.
[7]
Betz, V. and Rose, V. and Marquardt, A. Architecture and Cad for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.
[8]
Sparsø, J. and Furber, S. Principles of Asynchronous Circuit Design, Kluwer Academic Publishers, Boston, 2001.

Cited By

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  • (2010)Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computingInternational Journal of Reconfigurable Computing10.1155/2010/3524282010(1-11)Online publication date: 1-Jan-2010

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. FPGA
    2. PCHB
    3. a synchronous design
    4. logic cell

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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    • (2010)Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computingInternational Journal of Reconfigurable Computing10.1155/2010/3524282010(1-11)Online publication date: 1-Jan-2010

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