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Novel architectures for efficient (m, n) parallel counters

Published: 11 March 2007 Publication History

Abstract

Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3,2), (7,3), (15,4) and (31,5) counters capable of operating at ultra-low voltages are presented. Based on these counters, a generalized architecture is derived for large (m, n) parallel counters. The proposed architecture lays emphasis on the use of multiplexers and a combination of CMOS and transmission gate logic in arithmetic circuits that result in high speed and efficient design. The proposed counter designs have been compared with existing designs and are shown to achieve an improvement of about 45% in delay and a reduction of about 25% in power consumption.

References

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L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, Vol.34, pp.349--356, 1965.
[2]
E.E. Swartzlander,Jr. and R.F. Jones, Jr., "Digital Neural Network Implementation," Proceedings of the 11th Annual International Phoenix Conference on Computers and Communications, pp.722--728, 1992.
[3]
Earl E. Swartzlander, Jr., "A review of large parallel counter designs," Proceedings. IEEE Computer society Annual Symposium on VLSI, 2004, pp.89--98, Feb. 2004.
[4]
Earl E. Swartzlander, Jr., "Parallel Counters," IEEE Transactions on computers, Vol C-22, pp.1021--1024, Nov. 1973.
[5]
Robert F. Jones, Jr., and Earl E. Swartzlander, Jr., "Parallel Counter implementation" Journal of VLSI signal processing, vol. 7, pp. 223--232, 1994.
[6]
Mayur Mehta, Vijay Parmar and Earl E. Swartzlander, Jr., "High-speed Multiplier Design using Multi-Input Counter and Compressor Circuits," Proceedings 10t Symposium on Computer Arithmetic, Grenoble, France, pp. 43--50, 1991.
[7]
R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079--1090, July 1997.

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 11 March 2007

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      Author Tags

      1. high speed
      2. low power
      3. multiplexer
      4. parallel counters

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      March 11 - 13, 2007
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      • (2022)An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending用于图像融合基于混合全加器 和计数器的高效华莱士树型乘法器Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.210043223:6(950-965)Online publication date: 5-Jul-2022
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      • (2020)A novel high speed Low Latency Column Bit Compressed MAC architecture for Wireless Sensor Network applicationsComputer Communications10.1016/j.comcom.2019.11.013150:C(739-746)Online publication date: 15-Jan-2020
      • (2019)Multiplier Using NAND Based Compressors2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)10.1109/IEMENTech48150.2019.8981067(1-6)Online publication date: Aug-2019
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