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Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

Published: 11 March 2007 Publication History

Abstract

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown.

References

[1]
J. von Neumann, Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components, Automata Studies, Princeton University Press, 1956.
[2]
S. Roy and V. Beiu, Multiplexing Schemes for Cost-Effective Fault-Tolerance, 4th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 589--592, Aug. 2004.
[3]
Schmid and Y. Leblebici, Robust Circuit and System Design Methodologies for Nanometer-Scale Devices and Single-Electron Transistor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 11, pp. 1156--1166, Nov. 2004.
[4]
M. Stanisavljevic, A. Schmid, and Y. Leblebici, A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis, Proc. IEEE IFIP VLSI-SoC, October 2005.
[5]
M. Stanisavljevic, A. Schmid, Y. Leblebici, Fault-Tolerance of R Publication obust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density, International Joint Conference on Neural Networks, July 2006.
[6]
Publicly available parameters for the IBM 90nm technology http://www-03.ibm.com/chips/asics/products/stdcell.html
[7]
T. Schafbauer, et al., Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology, 2002 Symposium on VLSI Technology, June 2002.
[8]
Advanced Encryption Standard, Federal Information Processing Standards 197 (FIPS 197), National Institute of Standards and Technology (NIST), November 2001.

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  1. Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. fault-tolerant architecture
      2. high defect density
      3. reliability of submicron and nanoelectronic systems

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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