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Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Published: 11 March 2007 Publication History

Abstract

Deep submicron technology is expected to be plagued by many reliability issues including soft errors in logic. To address this, we demonstrate how exploiting the natural fault masking characteristics of logical functions can be achieved by exploring the design space for selecting subsets of cells from within a cell library prior to synthesis. Subset selection alone is shown to improve the reliability of combinational logic circuits by more than 35%. We compare how subset libraries effect the trade-offs between reliability, area, power, and performance. Further, we show that added benefits of reduced cell library size can benefit the design.

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Cited By

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  • (2014)Standard cell library tuning for variability tolerant designsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616886(1-6)Online publication date: 24-Mar-2014
  • (2014)Characterization technique to implement self-timed cells for VLSI design blocks2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)10.1109/ICEEE.2014.6978288(1-6)Online publication date: Sep-2014

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  1. Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      Publication History

      Published: 11 March 2007

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      Author Tags

      1. fault masking
      2. fault-tolerance
      3. reliability

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      View all
      • (2014)Standard cell library tuning for variability tolerant designsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616886(1-6)Online publication date: 24-Mar-2014
      • (2014)Characterization technique to implement self-timed cells for VLSI design blocks2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)10.1109/ICEEE.2014.6978288(1-6)Online publication date: Sep-2014

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