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A symmetric mos current-mode logic universal gate for high speed applications

Published: 11 March 2007 Publication History

Abstract

Mos Current Mode Logic (MCML) is a low-noise alternative toconventional CMOS for mixed-signal applications. The standard MCML Universal Gate is a utility circuit that can implement the basic logic operations (AND/NAND/OR/NOR). The asymmetric topology of the universal gates, however, reduces its operation frequency significantly. In this paper, a modified version of the standard universal gate is analyzed to quantify its advantages and drawbacks. When compared to the differential-pair universal gate, the modified topology has better output waveform, higher operation frequency and lower switching noise for the same power dissipation.

References

[1]
International Technology RoadMap for Semiconductors, "Radio frequency and analog/mixed-signal technologies for wireless communications," ITRS, Tech. Rep., 2005.
[2]
S. Khabiri and M. Shams, "An MCML four-bit ripple-carry adder design in 1 GHz range," in Proc. IEEE International Symposium on Circuits and Systems, vol. 2, May 2005, pp. 2326.
[3]
H. Hassan, M. Anis, M. Elmasry, "MOS current mode circuits: analysis, design, and variability," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885--898, August 2005.
[4]
S. Khabiri and M. Shams, "A mathematical programming approach to designing MOS current-mode logic circuits," in Proc. IEEE/ACM International Conference on Computer-Aided Design, vol. 51, May 2005, pp. 2425--2428.
[5]
O. Abdulkarim, "Design and optimization of Mos current-mode logic circuits," Master's thesis, Carleton University, Ottawa, Canada, 2006.
[6]
Behzad Razavi, Design of analog CMOS integrated circuits. Boston, MA: McGraw-Hill, 2001.

Cited By

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  • (2018)An efficient delay model for MOS current-mode logic automated design and optimizationIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203925857:8(2041-2052)Online publication date: 13-Dec-2018
  • (2018)Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computingCluster Computing10.1007/s10586-018-1917-5Online publication date: 15-Feb-2018
  • (2014)MOS Current Mode Logic Near Threshold CircuitsJournal of Low Power Electronics and Applications10.3390/jlpea40201384:2(138-152)Online publication date: 11-Jun-2014
  • Show More Cited By

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  1. A symmetric mos current-mode logic universal gate for high speed applications

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 11 March 2007

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      Author Tags

      1. ASIC
      2. MCML
      3. SCL
      4. VLSI

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      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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      View all
      • (2018)An efficient delay model for MOS current-mode logic automated design and optimizationIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203925857:8(2041-2052)Online publication date: 13-Dec-2018
      • (2018)Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computingCluster Computing10.1007/s10586-018-1917-5Online publication date: 15-Feb-2018
      • (2014)MOS Current Mode Logic Near Threshold CircuitsJournal of Low Power Electronics and Applications10.3390/jlpea40201384:2(138-152)Online publication date: 11-Jun-2014
      • (2011)The layout implementations of high-speed low-power MCML cells2011 International Conference on Electronics, Communications and Control (ICECC)10.1109/ICECC.2011.6067866(2936-2939)Online publication date: Sep-2011

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