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A design kit for a fully working shared memory multiprocessor on FPGA

Published: 11 March 2007 Publication History

Abstract

This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properlyallsynchronize the local copies with the shared memory image. This idea can be applied both to a scratchpad-based architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset.

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Cited By

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  • (2016)A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems10.1109/MIXDES.2016.7529783(443-447)Online publication date: Jun-2016
  • (2014)Accelerating Parallel Computations with OpenMP-Driven System-on-Chip Generation for FPGAsProceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs10.1109/MCSoC.2014.30(149-156)Online publication date: 23-Sep-2014
  • (2013)Prototyping hardware support for irregular applicationsProceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2432516.2432520(1-8)Online publication date: 21-Jan-2013
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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. FPGA
    2. embedded computing
    3. programming model
    4. reconfigurable logic
    5. shared memory

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    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Cited By

    View all
    • (2016)A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems10.1109/MIXDES.2016.7529783(443-447)Online publication date: Jun-2016
    • (2014)Accelerating Parallel Computations with OpenMP-Driven System-on-Chip Generation for FPGAsProceedings of the 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs10.1109/MCSoC.2014.30(149-156)Online publication date: 23-Sep-2014
    • (2013)Prototyping hardware support for irregular applicationsProceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2432516.2432520(1-8)Online publication date: 21-Jan-2013
    • (2013)μC-OS II-based Operating System design for cluster in NoC-based MPSoC2013 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2013)10.1109/ICSPCC.2013.6664028(1-5)Online publication date: Aug-2013
    • (2012)Design of a multi-soft-core based Laser Marking controller2012 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2012.6416737(1-6)Online publication date: Dec-2012
    • (2010)A reconfigurable multiprocessor architecture for a reliable face recognition implementationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871004(319-322)Online publication date: 8-Mar-2010
    • (2010)Scalability of a Parallel JPEG Encoder on Shared Memory ArchitecturesProceedings of the 2010 39th International Conference on Parallel Processing10.1109/ICPP.2010.58(502-507)Online publication date: 13-Sep-2010
    • (2010)A Compact Transactional Memory Multiprocessor System on FPGAProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.113(578-581)Online publication date: 31-Aug-2010
    • (2010)A reconfigurable multiprocessor architecture for a reliable face recognition implementation2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)10.1109/DATE.2010.5457185(319-322)Online publication date: Mar-2010
    • (2009)HW/SW methodologies for synchronization in FPGA multiprocessorsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508174(265-268)Online publication date: 24-Feb-2009
    • Show More Cited By

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