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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Published: 11 March 2007 Publication History

Abstract

This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SET-induced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm2/mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

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Cited By

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  • (2022)A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable DesignsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316808269:7(2721-2729)Online publication date: Jul-2022
  • (2022)Single Event Soft ErrorsNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_6(81-111)Online publication date: 1-Sep-2022
  • (2020)SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults ConsiderationsTechnologies10.3390/technologies80100058:1(5)Online publication date: 10-Jan-2020
  • Show More Cited By

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  1. Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. critical charge
    2. single event transient
    3. soft error

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    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2022)A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable DesignsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316808269:7(2721-2729)Online publication date: Jul-2022
    • (2022)Single Event Soft ErrorsNoise Contamination in Nanoscale VLSI Circuits10.1007/978-3-031-12751-9_6(81-111)Online publication date: 1-Sep-2022
    • (2020)SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults ConsiderationsTechnologies10.3390/technologies80100058:1(5)Online publication date: 10-Jan-2020
    • (2020)A Physics-Based Single Event Transient Pulse Width Model for CMOS VLSI CircuitsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2020.302328520:4(723-730)Online publication date: Dec-2020
    • (2018)An Efficient Model for Soft Error Vulnerability of Dynamic CircuitsComputer Engineering and Technology10.1007/978-981-10-7844-6_13(133-142)Online publication date: 3-Jan-2018
    • (2016)Single event coupling delay estimation in nanometer technologiesAnalog Integrated Circuits and Signal Processing10.1007/s10470-015-0670-486:2(215-225)Online publication date: 1-Feb-2016
    • (2016)Modeling Single Event Crosstalk Noise in Nanometer TechnologiesSoft Error Mechanisms, Modeling and Mitigation10.1007/978-3-319-30607-0_5(49-62)Online publication date: 26-Feb-2016
    • (2015)Modeling single event crosstalk speedup in nanometer technologiesMicroelectronics Journal10.1016/j.mejo.2015.02.00246:5(343-350)Online publication date: May-2015
    • (2014)Coupling induced soft error mechanisms in nanoscale CMOS technologiesAnalog Integrated Circuits and Signal Processing10.1007/s10470-013-0216-679:1(115-126)Online publication date: 1-Apr-2014
    • (2011)Modeling Single Event Crosstalk in Nanometer TechnologiesIEEE Transactions on Nuclear Science10.1109/TNS.2011.216529558:5(2493-2502)Online publication date: Oct-2011
    • Show More Cited By

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