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A new decompression system for the configuration process of SRAM-based FPGAS

Published: 11 March 2007 Publication History

Abstract

Nowadays Field Programmable Gate Arrays (FPGAs) are an improved technology for developing high-performance embedded systems. SRAM-based FPGAs offers the possibility of in-the-field reconfiguration that results in the ability to adapt the product to modified user's requirements, to enrich the product's features, or simply to correct bugs. With the advent of multi-million gate FPGAs, the size of the configuration information that defines what circuit the FPGA implements has increased drastically, and thus the amount of external memory needed to keep the configuration data is increasing dramatically. In this work we developed a novel configuration compression system that exploits internal configuration mechanism of modern SRAM-based FPGAs and results in high compression efficiency. The proposed system is applicable to any modern SRAM-based FPGA devices having an embedded microprocessor core since the configuration data are processed as raw data. Moreover, the proposed approach does not require any external hardware support and allows high speed dynamic reconfiguration. Experimental results on Xilinx SRAM-based FPGAs platform implementing several real-world circuits demonstrated 82% savings in memory on the average.

References

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Xilinx Product Specification, "Virtex-II Platform FPGAs: Complete Data Sheet," DS031 (v3.4) March 1, 2005.
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A. Khu, "Xilinx FPGA Configuration Data Compression and Decompression," Xilinx - WP152, September 2001.
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Z. Li and S. Hauck, "Configuration compression for Virtex FPGAs," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 111--119, 2001.
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Altera sheets, "Using Altera Enhanced Configuration Devices," Chapter 14, April 2003.
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Cited By

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  • (2018)Multi-level reconfigurable architectures in the switch modelJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2009.11.00856:2-3(103-115)Online publication date: 29-Dec-2018
  • (2014)A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory ErrorsIEEE Embedded Systems Letters10.1109/LES.2014.23544546:4(77-80)Online publication date: Dec-2014

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  1. A new decompression system for the configuration process of SRAM-based FPGAS

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 11 March 2007

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    Author Tags

    1. SRAM-based FPGA
    2. compression algorithm
    3. configuration mechanisms

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    March 11 - 13, 2007
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    View all
    • (2018)Multi-level reconfigurable architectures in the switch modelJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2009.11.00856:2-3(103-115)Online publication date: 29-Dec-2018
    • (2014)A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory ErrorsIEEE Embedded Systems Letters10.1109/LES.2014.23544546:4(77-80)Online publication date: Dec-2014

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