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Minimizing peak power in synchronous logic circuits

Published: 11 March 2007 Publication History

Abstract

Minimizing peak power decreases the probability of failure due to hot carrier effects and electromigration. It also reduces the maximum IR voltage drop, the magnitude of substrate noise, and packaging costs. In mobile applications, minimizing peak power can help reduce the battery size. In synchronous circuits the peak power draw is correlated with clock transitions when the entire clock distribution network, all of the flip-flops and their immediate fanout switch simultaneously. In this paper, we propose an efficient, deterministic method for finding the optimal distribution of clock latencies for minimizing peak power consumption. Our algorithm spreads the clock transitions using timing slacks on non-critical paths and preserves the circuit performance. We validate our method by transistor level simulations on benchmark circuits. These experiments show that our method can reduce the peak power consumption up to 55 percent in circuits whose peak power is due to simultaneous clock transitions.

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Cited By

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  • (2010)Peak current reduction by simultaneous state replication and re-encodingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133554(592-595)Online publication date: 7-Nov-2010
  • (2010)Peak current reduction by simultaneous state replication and re-encoding2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5654204(592-595)Online publication date: Nov-2010
  • (2008)Power efficient DSP datapath configuration methodology for FPGA2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629997(515-518)Online publication date: Sep-2008

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 11 March 2007

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      Author Tags

      1. clock scheduling
      2. peak power
      3. power optimization

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      Cited By

      View all
      • (2010)Peak current reduction by simultaneous state replication and re-encodingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133554(592-595)Online publication date: 7-Nov-2010
      • (2010)Peak current reduction by simultaneous state replication and re-encoding2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5654204(592-595)Online publication date: Nov-2010
      • (2008)Power efficient DSP datapath configuration methodology for FPGA2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629997(515-518)Online publication date: Sep-2008

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