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Modeling and estimating leakage current in series-parallel CMOS networks

Published: 11 March 2007 Publication History

Abstract

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.

References

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J. H. Anderson and F. N. Najm, "Active Leakage Power Optimization for FPGAs," IEEE Trans. on CAD, vol. 25, no. 3, Mar. 2006, pp. 423--437.
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S. Yang, W. Wolf, N. Vijaykrishnan, Y. Xie and W. Wang, "Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits," Proc. Int. Conference on VLSI Design, Jan. 2005, pp. 165--170.
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S. Gavrilov, A. Glebov, S. Pullela, S. C. Moore, A. Dharchoudhury, R. Panda, G. Vijayan and D. T. Blaauw, "Library-less Synthesis for Static CMOS Combinational Logic Circuits," Proc. ICCAD, Nov. 1997, pp. 658--662.
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Z. Cheng, M. Johnson, L. Wei and K. Roy, "Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks," Proc. Int. Symposium Low Power Electronics and Design, Aug. 1998, pp. 239--244.
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K. Roy and S. Prasad, "Low-Power CMOS VLSI Circuit Design," John Wiley & Sons, 2000.
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S. G. Narendra and A. Chandrakasan, "Leakage in Nanometer CMOS Technologies," Springer, 2006.
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D. Lee, W. Kwong, D. Blaauw and D. Sylvester, "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage," Proc. DAC, June 2003, pp.175--180.
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Cited By

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  • (2008)Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanismsProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366207(407-410)Online publication date: 4-May-2008
  • (2007)Modeling Subthreshold Leakage Current in General Transistor NetworksProceedings of the IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2007.68(512-513)Online publication date: 9-Mar-2007

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  1. Modeling and estimating leakage current in series-parallel CMOS networks

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. CMOS gates
      2. leakage current modeling
      3. static power dissipation

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      March 11 - 13, 2007
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      Cited By

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      • (2008)Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanismsProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366207(407-410)Online publication date: 4-May-2008
      • (2007)Modeling Subthreshold Leakage Current in General Transistor NetworksProceedings of the IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2007.68(512-513)Online publication date: 9-Mar-2007

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