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Analyzing and modeling process balance for sub-threshold circuit design

Published: 11 March 2007 Publication History

Abstract

This paper describes the strong effects on sub-threshold digital circuit operation of the ratio of PMOS and NMOS current in a given process. We define the concept of process balance/imbalance as describing this ratio and explain the impact ofdifferent circuit and environmental parameters on processbalance. Many of these characteristics are best understood by the degree to which they increase or further decrease process balance. We also propose a model that provides accurate estimation of the effects of process balance that is useful for understanding the impact of process variations and the appropriate types of circuits to use for sub-threshold operation in a given process.

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. minimum energy operation
      2. process balance
      3. process imbalance
      4. sub-threshold digital circuits
      5. sub-threshold modeling

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      March 11 - 13, 2007
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      View all
      • (2024)A brief Survey of Ultra-Low-Voltage CMOS: Approaching the Diffusion Limit2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS60203.2024.10506162(1-5)Online publication date: 27-Feb-2024
      • (2016)Analysis & design of robust ultra-low power subthreshold SRAM models2016 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)10.1109/ICCICCT.2016.7987945(200-204)Online publication date: Dec-2016
      • (2015)MOSFET aspect ratio optimization for minimized transistor mismatch at UDSM technology nodes2015 International Conference on Computer Communication and Informatics (ICCCI)10.1109/ICCCI.2015.7218134(1-4)Online publication date: Jan-2015
      • (2010)Flexible Circuits and Architectures for Ultralow PowerProceedings of the IEEE10.1109/JPROC.2009.203721198:2(267-282)Online publication date: Mar-2010
      • (2009)Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold DesignsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.5555/1506784.1506787(11-20)Online publication date: 30-Jan-2009
      • (2009)Sub-threshold circuit design with shrinking CMOS devices2009 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2009.5118319(2541-2544)Online publication date: May-2009
      • (2009)Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold DesignsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-95948-9_2(11-20)Online publication date: 2009
      • (2009)Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOSNanosystems Design and Technology10.1007/978-1-4419-0255-9_3(45-84)Online publication date: 21-May-2009
      • (2008)Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479712(127-132)Online publication date: Mar-2008
      • (2007)Statistical modeling for the minimum standby supply voltage of a full SRAM arrayESSCIRC 2007 - 33rd European Solid-State Circuits Conference10.1109/ESSCIRC.2007.4430327(400-403)Online publication date: Sep-2007

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