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Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint

Published: 11 March 2007 Publication History

Abstract

Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard cell implementation of the template based QDI circuits utilizing standard layout generation tools. This is achieved by analyzing and removing outer cell isochronic fork constraint which is the main timing constraints limiting the standard layout generation. The isochronic fork free final netlist has 10--20% area overhead in average which is the cost of facilitating the use of standard CAD tools.

References

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Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura: The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller. ASYNC 2003.
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S. B. Furber, D. A. Edwards and J. D. Garside AMULET3: a 100 MIPS Asynchronous Embedded Processor. ICCD'00 17-20th September 2000.
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http://www.async.ir
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A. J. Martin, "Compiling communicating processes into delay-insensitive VLSI circuits," Distributed Computing, vol. 1, no. 4, pp. 226--234, 1986.
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Andrew M. Lines. Pipelined asynchronous circuits. Master's thesis, California Institute of Technology, Computer Science Department, 1995. CS-TR-95-21.
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Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel: High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. ASYNC 2004: 95--105.
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J. Sparso, S. Furber, "Principles of Asynchronous Circuit Design - A System Perspective," Kluwer Academic Publishers, 2002.

Cited By

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  • (2012)A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous CircuitsProceedings of the 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2012.29(73-80)Online publication date: 7-May-2012
  • (2011)Templated-Based Asynchronous Design for Testable and Fail-Safe OperationProceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems10.1109/DFT.2011.63(146-152)Online publication date: 3-Oct-2011
  • (2009)High performance asynchronous design flow using a novel static performance analysis methodComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02535:6(920-941)Online publication date: 1-Nov-2009
  • Show More Cited By

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. asynchronous circuits
    2. quasi-delay insensitive
    3. standard-cell layout

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    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2012)A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous CircuitsProceedings of the 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2012.29(73-80)Online publication date: 7-May-2012
    • (2011)Templated-Based Asynchronous Design for Testable and Fail-Safe OperationProceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems10.1109/DFT.2011.63(146-152)Online publication date: 3-Oct-2011
    • (2009)High performance asynchronous design flow using a novel static performance analysis methodComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02535:6(920-941)Online publication date: 1-Nov-2009
    • (2009)An EDA tool for implementation of low power and secure crypto-chipsComputers and Electrical Engineering10.1016/j.compeleceng.2008.06.01435:2(244-257)Online publication date: 1-Mar-2009
    • (2008)An Efficient Fault Simulator for QDI Asynchronous Circuits2008 4th Southern Conference on Programmable Logic10.1109/SPL.2008.4547739(99-104)Online publication date: Mar-2008
    • (2008)A novel test environment for template based QDI asynchronous circuits2008 15th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2008.4674906(526-529)Online publication date: Aug-2008

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