skip to main content
10.1145/1228784.1228863acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Utilizing custom registers in application-specific instruction set processors for register spills elimination

Published: 11 March 2007 Publication History

Abstract

Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration, e.g., automatic custom instruction identification and synthesis, the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach and a linear scan register allocation algorithm to utilize the existing custom registers in ASIPs for eliminating register spills. The data traffic between the processor and memory can be reduced through efficient on-chip communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that a promising performance gain can be achieved, which is orthogonal to improvements by any other technique in ASIP design.

References

[1]
Tensilica Inc. {http://www.tensilica.com}.
[2]
ARC International. {http://www.arc.com}.
[3]
Improv Systems Inc. {http://www.improvsys.com}.
[4]
Altera Corp. {http://www.altera.com}.
[5]
Xilinx Inc. {http://www.xilinx.com}.
[6]
ASIP Meister. {http://www.eda-meister.org/asipmeister}.
[7]
SimpleScalar Portable Instruction Set Architecture (PISA). {http://www.simplescalar.com/}.
[8]
T. Austin, E. Larson, and D. Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEE Micro, 35(2):59--67, Feb. 2002.
[9]
N. Clark, M. Kudlur, H. Park, S. Mahlke, and K. Flautner. Application-specific processing on a general-purpose core via transparent instruction set customization. In Proc. Int. Symp. Microarchitecture, pages 30--40, Nov. 2004.
[10]
J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman, and Z. Zhang. Instruction set extension with shadow registers for configurable processors. In ACM Proc. Int. Symp. on Field-Programmable Gate Arrays, pages 99--106, Feb. 2005.
[11]
J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. In ACM Proc. Int. Symp. on Field-Programmable Gate Arrays, pages 183--189, Feb. 2004.
[12]
J. Cong, G. Han, and Z. Zhang. Architecture and compilation for data bandwidth improvement in configurable embedded processors. In Proc. Int. Conf. Computer-Aided Design, pages 263--270, Nov. 2005.
[13]
D. Fischer, J. Teich, M. Thies, and R. Weper. Efficient architecture/compiler co-exploration for ASIPs. In Int. Conf. Compilers, Architecture, & Synthesis for Embedded Systems, pages 27--34, Oct. 2002.
[14]
R. E. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20(2):60--70, Mar./Apr. 2000.
[15]
D. Goodwin and D. Petkov. Automatic generation of application specific processors. In Int. Conf. Compilers, Architecture, & Synthesis for Embedded Systems, pages 137--147, Oct. 2003.
[16]
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE Int. WkShp on Workload Characterization, pages 3--14, Dec. 2001.
[17]
R. Kastner, A. Kaplan, S. Ogrenci Memik, and E. Bozorgzadeh. Instruction generation for hybrid reconfigurable systems. ACM Trans. Design Automation of Electronic Systems, 7(4):605--627, Oct. 2002.
[18]
K. Keutzer, S. Malik, and A. R. Newton. From ASIC to ASIP: The next design discontinuity. In Proc. Int. Conf. Computer Design, pages 84--90, Sept. 2002.
[19]
M. Poletto and V. Sarkar. Linear scan register allocation. ACM Transactions on Programming Languages and Systems, 21(5):895--913, Sept. 1999.
[20]
L. Pozzi, K. Atasu, and P. Ienne. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Computer-Aided Design of Integrated Circuits, 25(7):1209--1229, July 2006.
[21]
S. Skiena. Maximum independent set. In Implementing discrete mathematics: Combinatorics and graph theory with Mathematica, pages 218--219. MA: Addison-Welsey, 1990.
[22]
F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Custom-instruction synthesis for extensible processor platform. IEEE Trans. Computer-Aided Design of Integrated Circuits, 23(2):216--228, Feb. 2004.
[23]
L. Wehmeyer, M. K. Jain, S. Steinke, P. Marwedel, and M. Balakrishnan. Analysis of the influence of register file size on energy consumption, code size, and execution time. IEEE Trans. Computer-Aided Design of Integrated Circuits, 20(11):1329--1337, Nov. 2001.
[24]
P. Yu and T. Mitra. Characterizing embedded applications for instruction-set extensible processors. In Proc. Design Automation Conf., pages 723--728, June 2004.

Cited By

View all
  • (2014)Register spilling for specific application domains in ASIPs7th International Conference on Information and Automation for Sustainability10.1109/ICIAFS.2014.7069539(1-5)Online publication date: Dec-2014
  • (2011)Processor Accelerator Customization through Data Flow Graph ExplorationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.1540E94-A:7(1540-1552)Online publication date: 2011
  • (2009)Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor SynthesisIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.2283E92-A:9(2283-2294)Online publication date: 2009
  • Show More Cited By

Index Terms

  1. Utilizing custom registers in application-specific instruction set processors for register spills elimination

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 March 2007

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. ASIP
    2. custom register
    3. register file

    Qualifiers

    • Article

    Conference

    GLSVLSI07
    Sponsor:
    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 27 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2014)Register spilling for specific application domains in ASIPs7th International Conference on Information and Automation for Sustainability10.1109/ICIAFS.2014.7069539(1-5)Online publication date: Dec-2014
    • (2011)Processor Accelerator Customization through Data Flow Graph ExplorationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.1540E94-A:7(1540-1552)Online publication date: 2011
    • (2009)Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor SynthesisIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.2283E92-A:9(2283-2294)Online publication date: 2009
    • (2008)Thermal-aware Design Considerations for Application-Specific Instruction Set ProcessorProceedings of the 2008 Symposium on Application Specific Processors10.1109/SASP.2008.4570787(63-68)Online publication date: 8-Jun-2008
    • (2008)Memory Models for an Application-Specific Instruction-set Processor Design FlowProceedings of the 2008 International Conference on Embedded Software and Systems10.1109/ICESS.2008.40(471-478)Online publication date: 29-Jul-2008

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media