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A design methodology for space-time adapter

Published: 11 March 2007 Publication History

Abstract

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism&), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

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Cited By

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  • (2014)A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2014.7050092(742-745)Online publication date: Dec-2014
  • (2011)High-Level Synthesis: On the path to ESL design2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157400(1098-1101)Online publication date: Oct-2011

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 March 2007

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Author Tags

  1. RTL design
  2. communication and interface synthesis
  3. digital signal processing and multimedia applications

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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Cited By

View all
  • (2014)A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2014.7050092(742-745)Online publication date: Dec-2014
  • (2011)High-Level Synthesis: On the path to ESL design2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157400(1098-1101)Online publication date: Oct-2011

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