skip to main content
10.1145/1228784.1228873acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects

Published: 11 March 2007 Publication History

Abstract

Inductance effects cannot be neglected in global interconnect lines as well as in circuits operating at higher frequencies. This paper presents a new spatio-temporal bus-encoding technique to minimize simultaneous switching noise as well as reduce delay and power dissipation in on-chip buses where inductance effects are dominating. Simulation experiments are carried out to find out the delay and SSN reduction for interconnect lines of different lengths (2mm, 5mm and 10mm) at various technology nodes (180nm, 130nm, 90nm and 65nm). Results obtained show that that the proposed bus-encoding scheme provides a delay reduction of about 54% to 73% with respect to the worst case delay. In addition, encoding is combined with wire shaping and its impact on further delay reduction is observed to be 4% to 26%. Further, when encoding was combined with wire shaping and repeater insertion, an additional delay reduction of 9% to 33% is observed. Concerning SSN, the encoding scheme is tested with various SPEC'95 benchmarks and it is found that SSN is reduced by about 33% on an average compared with the un-encoded data. Finally, energy minimization of about 13% on an average is achieved by the application of new spatio-temporal encoding scheme as reflected by the SPEC'95 bench mark tests.

References

[1]
Semiconductor Industry Association, International Technology Roadmap For Semiconductors. Website: http://www.itrs.net/.
[2]
Shang-Wei Tu, Jing-Yang Jou and Yao-Wen Chang, "RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction," IEEE Transactions on CAD (2720), October 2006.
[3]
P. Sotiriadis and A. Chandrakasan, "Reducing bus delay in sub-micron technology using coding," Proceedings of IEEE Asia and South Pacific Design Automation Conf (ASPDAC'01), pp 109--114, 2000.
[4]
B. Victor and K. Keutzer, "Bus Encoding to Prevent Crosstalk Delay," ICCAD, 2001, pp. 57--63.
[5]
Lin Li, Vijaykrishnan.N, Kandemir.M and Irwin.M.J., "A Crosstalk Aware Interconnect with Variable Cycle Transmission," Proceeding of DATE, 2004, pp. 102--107.
[6]
Lampropoulos, M., Al-Hashimi, B. and Rosinger, P., "Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique," Proceedings of DATE, pp. 1372--1373, Feb 2004.
[7]
K.S. Sainarayanan, J.V.R. Ravindra, M.B. Srinivas, "Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method," DELTA 2006, pp 336--339.
[8]
B.J. LamMeres and S.P. Khatri, "Encoding-Based Minimization of Inductive Cross-talk For Off-chip Data Transmission," Proceedings of DATE, pp. 1318--1323, March 2005.
[9]
Stephen C.Thierauf, High-speed Circuit Board Signal Integrity, Artech House Publishers, March 2004.
[10]
Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall PTR, June 2003.
[11]
A. P. Chandrakasan and R. W. Brodersen, Low PowerDigital CMOS Design, Kluwer Academic Publisher, 1995.
[12]
Stephen H. Hall, Garrett W. Hall and James A. McCall, High-Speed Digital System Design. John Wiley and Sons Inc., 2000.
[13]
Predictive technology model, NIMO Group, ASU. http://www.eas.asu.edu/~ptm/interconnect.html.
[14]
Mircea R. Stan and Wayne P. Burleson, "Bus InvertCoding For Low Power I/O," IEEE Trans. on VLSI Systems, pp. 49--58, March 1995.
[15]
KW Kim, KH Back, N. Shanbhag, CL Liu, and SM Kang "Coupling-driven signal encoding scheme for low-power interface design," Proceedings of IEEE ICCAD, pp. 318--321, Nov. 2000.
[16]
M. A. El-Moursy and Friedman, E.G., "Optimum Wire Shaping of an RLC Interconnect," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, December 2003.
[17]
Yehea I. Ismail et al., "Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect," In Proceedings of the IEEE ASIC Conference, pp 369--373, Sep 1998.

Cited By

View all
  • (2016)Stochastic model based dynamic power estimation of microprocessor using Imperas simulator2016 Annual IEEE Systems Conference (SysCon)10.1109/SYSCON.2016.7490564(1-8)Online publication date: Apr-2016
  • (2015)Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnectsJournal of Engineering, Design and Technology10.1108/JEDT-05-2013-004013:3(486-498)Online publication date: 6-Jul-2015
  • (2011)Encoding in VLSI InterconnectsAdvances in Wireless, Mobile Networks and Applications10.1007/978-3-642-21153-9_24(260-269)Online publication date: 2011
  • Show More Cited By

Index Terms

  1. Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. bit transitions
      2. bus-encoding scheme
      3. crosstalk noise
      4. decoder
      5. delay
      6. encoder
      7. high impedance state
      8. inductive coupling
      9. low power
      10. simultaneous switching noise (SSN)
      11. spatial and temporal redundancy

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)1
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2016)Stochastic model based dynamic power estimation of microprocessor using Imperas simulator2016 Annual IEEE Systems Conference (SysCon)10.1109/SYSCON.2016.7490564(1-8)Online publication date: Apr-2016
      • (2015)Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnectsJournal of Engineering, Design and Technology10.1108/JEDT-05-2013-004013:3(486-498)Online publication date: 6-Jul-2015
      • (2011)Encoding in VLSI InterconnectsAdvances in Wireless, Mobile Networks and Applications10.1007/978-3-642-21153-9_24(260-269)Online publication date: 2011
      • (2009)Crosstalk avoidance and error-correction coding for coupled RLC interconnects2009 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2009.5117705(141-144)Online publication date: May-2009
      • (2008)Inter-Wire Coupling Reduction Analysis of Bus-Invert CodingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2008.91819755:7(1911-1920)Online publication date: Aug-2008
      • (2008)Encoding Techniques for On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00007-4(253-300)Online publication date: 2008

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media