skip to main content
10.1145/1228784.1228881acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

Published: 11 March 2007 Publication History

Abstract

The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed for verifying or grading functional test programs capabilities employing traditional techniques is huge and constitutes a serious bottleneck in the test flow. In this paper we propose a new mechanism for grading functional test program path-delay coverage (1) relying on FPGA-based emulation, (2) based on suitable instrumentation of the circuit structure and (3) exploiting ad hoc modules to minimize the host performance requirements stemming from the experiment management. The proposed setup reduces the grading time by several orders of magnitude with respect to software environments. Moreover, the experimented mechanism is capable of pinpointing the clock cycles when path activation arises, thus providing a key for relating excitation conditions to the executed instructions.

References

[1]
M. Abramovici, P. Menon, Fault simulation on reconfigurable hardware, IEEE Symposium on FPGAs for Custom Computing Machines, 1997, 182--190.
[2]
M.J. Bushnell, V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
[3]
T.J. Chakraborty, V.D. Agrawal, L. Bushnell, Path delay fault simulation of sequential circuits, IEEE Trans. on VLSI Systems, vol. 8, n. 2, April 2000, 223--228.
[4]
K.T. Cheng, H.C. Chen, Classification and identification of nonrobust untestable path delay faults, IEEE Trans. on CAD, vol. 15, n. 8, Aug. 1996, 845--853.
[5]
K.T. Cheng, S.Y. Huang, W.J. Dai, Fault emulation: A new methodology for fault grading, IEEE Trans. on CAD, Volume 18, n. 10, October 1999, 1487--1495.
[6]
W.-T. Cheng, M.-L. Yu, Differential fault simulation for sequential circuits, Journal of Electronic Testing: Theory and Appl., vol. 1, Feb. 1990, 7--13.
[7]
M.A. Gharaybeh, M.L. Bushnell, V.D. Agrawal, Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests, Journal of Electronic Testing: Theory and Appl., vol. 11, n. 1, Aug. 1997, 55--67.
[8]
S. Kang, Efficient path-delay fault simulation for standard scan design, IEEE Proceedings on Circuits, Devices and Systems, Vol. 149, n. 56, Oct.-Dec. 2002, 315--320.
[9]
C.J. Lin, S.M. Reddy, On Delay Fault Testing in Logic Circuits, IEEE Trans. on CAD, vol. 6, n. 5, Sep. 1987, 694--703.
[10]
S. Natarajan, S. Patil, S. Chakravarty, Path delay fault simulation on large industrial designs, IEEE VLSI Test Symposium, 2006, 16--21.
[11]
T. M. Nierman, W.-T. Cheng, J. H. Patel, PROOFS: A fast memory efficient sequential circuit fault simulator, IEEE Trans. on CAD, vol. 11, Feb. 1992, 198--207.
[12]
M. H. Schulz, F. Fink, K. Fuchs, Parallel pattern fault simulation of path delay faults, ACM/IEEE Design Automation Conf., 1989, 357--363.
[13]
R. Sedaghat, A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation, IEEE International Symposium on Circuits and Systems, vol. 5, 2003, 213--216.
[14]
R. Sedaghat, Routability estimation of FPGA-based fault injection, IEEE Canadian Conference on Electrical and Computer Engineering, vol. 1, 2003, 129--132.
[15]
A. Virazel, R. David, P. Girard, C. Landrault, S. Prassoudovitch, Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences, IEEE European Test Workshop, 2000, 9--14.
[16]
L. Wei-Cheng, A. Krstic, K.T. Cheng, Functionally testable path delay faults on a microprocessor, IEEE Design & Test of Computers, vol. 17, n. 4, Oct.-Dec. 2000, 6--14.
[17]
http://www.opencores.org

Cited By

View all
  • (2015)Enabling GPGPU Low-Level Hardware Explorations with MIAOWACM Transactions on Architecture and Code Optimization10.1145/276490812:2(21:1-21:25)Online publication date: 24-Jun-2015
  • (2012)Emulation in post-silicon validation: It's not just for functionality anymore2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2012.6418252(110-117)Online publication date: Nov-2012
  • (2010)A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation2010 IEEE International Test Conference10.1109/TEST.2010.5699267(1-10)Online publication date: Nov-2010
  • Show More Cited By

Index Terms

  1. Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. FPGA
      2. fault-emulation
      3. path-delay
      4. software-based testing

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2015)Enabling GPGPU Low-Level Hardware Explorations with MIAOWACM Transactions on Architecture and Code Optimization10.1145/276490812:2(21:1-21:25)Online publication date: 24-Jun-2015
      • (2012)Emulation in post-silicon validation: It's not just for functionality anymore2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2012.6418252(110-117)Online publication date: Nov-2012
      • (2010)A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation2010 IEEE International Test Conference10.1109/TEST.2010.5699267(1-10)Online publication date: Nov-2010
      • (2009)Delay Fault Diagnosis in Sequential CircuitsProceedings of the 2009 Asian Test Symposium10.1109/ATS.2009.16(355-360)Online publication date: 23-Nov-2009
      • (2008)On efficient generation of instruction sequences to test for delay defects in a processorProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366178(279-284)Online publication date: 4-May-2008
      • (2007)On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor CoresProceedings of the 12th IEEE European Test Symposium10.1109/ETS.2007.28(179-184)Online publication date: 20-May-2007

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media